Cell operation methods using gate-injection for floating gate nand flash memory

• US 20080080248A1
• Filed: 10/03/2006
• Published: 04/03/2008
• Est. Priority Date: 10/03/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hsu, Tzu-Hsuan, Lai, Erh-Kun, Lue, Hang-Ting
• Granted Patent: US 8,325,530 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

Claims

1. A method of performing an operation on a flash memory cell device, the device having a gate coupling ratio between a floating gate and a control gate of less than about 0.4, the method comprising:

(a) providing a potential across the control gate; and

(b) injecting electrons to the floating gate from the control gate or ejecting electrons from the floating gate to the control gate.

2. A method of performing an operation on a flash memory cell device, the device having a bulk-tied FinFET-like structured silicon channel, and having a gate coupling ratio between a floating gate and a control gate of less than about 0.4, the method comprising:

(a) providing a potential across the control gate; and

(b) injecting electrons to the floating gate from the control gate or ejecting electrons from the floating gate to the control gate.

3. The method of claim 2, wherein the silicon channel is an n-channel type, and step (b) further comprises:

(i) programming the cell by ejecting electrons from the floating gate to the control gate; and

(ii) erasing the cell by injecting electrons to the floating gate from the control gate.

4. The method of claim 2, wherein the silicon channel is a p-channel type, and step (b) further comprises:

(i) programming the cell by injecting electrons to the floating gate from the control gate; and

(ii) erasing the cell by ejecting electrons from the floating gate to the control gate.

5. A method of performing an operation on a flash memory cell device provided in a NAND flash memory array, the device having a bulk-tied FinFET-like structured silicon channel, and having a gate coupling ratio between a floating gate and a control gate of less than about 0.4, the method comprising:

(a) providing a potential across the control gate; and

(b) injecting electrons to the floating gate from the control gate or ejecting electrons from the floating gate to the control gate.

6. The method of claim 5, wherein the silicon channel is an n-channel type, and step (b) further comprises:

(i) programming the cell by ejecting electrons from the floating gate to the control gate; and

(ii) erasing the cell by injecting electrons to the floating gate from the control gate.

7. The method of claim 5, wherein the silicon channel is a p-channel type, and step (b) further comprises:

(i) programming the cell by injecting electrons to the floating gate from the control gate; and

(ii) erasing the cell by ejecting electrons from the floating gate to the control gate.