MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE
First Claim
1. A system comprising:
- an integrated circuit buffer device including;
a first interface to receive write data and control information that indicates a write operation;
a second interface to convey the write data and the control information; and
a register to store a value that indicates a number of integrated circuit memory devices to receive, in response to the control information, the write data;
a first integrated circuit memory device to store a first portion of the write data;
a first signal path coupled to the second interface and the first integrated circuit memory device, the first signal path to convey the first portion of the write data from the integrated circuit buffer device to the first integrated circuit memory device;
a second integrated circuit memory device to store a second portion of the write data;
a second signal path coupled to the second interface and the second integrated circuit memory device, the second signal path to convey the second portion of the write data from the integrated circuit buffer device to the second integrated circuit memory device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.
1 Assignment
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Accused Products
Abstract
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
243 Citations
20 Claims
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1. A system comprising:
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an integrated circuit buffer device including;
a first interface to receive write data and control information that indicates a write operation;
a second interface to convey the write data and the control information; and
a register to store a value that indicates a number of integrated circuit memory devices to receive, in response to the control information, the write data;
a first integrated circuit memory device to store a first portion of the write data;
a first signal path coupled to the second interface and the first integrated circuit memory device, the first signal path to convey the first portion of the write data from the integrated circuit buffer device to the first integrated circuit memory device;
a second integrated circuit memory device to store a second portion of the write data;
a second signal path coupled to the second interface and the second integrated circuit memory device, the second signal path to convey the second portion of the write data from the integrated circuit buffer device to the second integrated circuit memory device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system comprising:
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an integrated circuit buffer device including;
a first interface to receive control information;
a second interface to output the control information and receive data; and
a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, provides a portion of the data from a corresponding memory access;
a first integrated circuit memory device to output a first portion of the data;
a first signal path coupled to the integrated circuit buffer device and the integrated circuit memory device, the first signal path to convey the first portion of the data from the first integrated circuit memory device to the integrated circuit buffer device;
a second integrated circuit memory device to output a second portion of the data;
a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey the second portion of data from the second integrated circuit memory device to the integrated circuit buffer device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.
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12. A system comprising:
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a first integrated circuit memory device and a second integrated circuit memory device;
an integrated circuit buffer device including;
a first interface to receive control information;
a second interface to output the control information and receive first data; and
registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices;
a first signal path coupled to the integrated circuit buffer device and the integrated circuit memory device, the first signal path to convey a first portion of the first data from the first integrated circuit memory device to the integrated circuit buffer device;
a second signal path coupled to the integrated circuit buffer device and the second integrated circuit memory device, the second signal path to convey a second portion first data from the second integrated circuit memory device to the integrated circuit buffer device; and
a third signal path coupled to the integrated circuit buffer device and the first and second integrated circuit memory devices, the third signal path to convey the control information from the integrated circuit buffer device to both the first and second integrated circuit memory devices.
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13. An integrated circuit buffer device including:
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a first interface to receive control information;
a second interface to output the control information and transfer first data associated with the control information; and
a register to store a value that indicates a number of integrated circuit memory devices to perform a memory access in response to the control information, wherein each memory device included in the number of integrated circuit memory devices, indicated by the value, transfers a portion of the data from a corresponding memory access. - View Dependent Claims (14, 15, 16, 17)
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18. A module comprising:
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a first integrated circuit memory device and a second integrated circuit memory device;
an integrated circuit buffer coupled to the first integrated circuit memory device and the second integrated circuit memory device, the integrated circuit buffer device including;
a first interface to receive control information;
a second interface to output the control information and receive first data; and
registers to store information indicating a number of signal paths, a number of signal lines included in each signal path of the number of signal paths coupled between the integrated circuit buffer device and each of the first and second integrated circuit memory devices.
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19. A method of operation in an integrated circuit device, the method comprising:
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receiving first control information that indicates a read operation of a plurality of integrated circuit memory devices having a first memory organization;
in response to the first control information, outputting second control information on a first signal path coupled to a first integrated circuit memory device having a second memory organization;
in response to the first control information, outputting third control information on the first signal path coupled to a second integrated circuit memory device, the second integrated circuit memory device having the second memory organization;
receiving first read data from the first integrated circuit memory device, the first read data being provided by the first integrated circuit memory device in response to the second control information;
receiving second read data from the second integrated circuit memory device, the second read data being provided by the second integrated circuit memory device in response to the third control information; and
outputting read data including the first and second read data to a memory controller.
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20. A buffer circuit comprising:
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means for receiving control information that indicates a read operation of a first plurality of integrated circuit memory devices having a first memory organization; and
means for providing read data from a second plurality of integrated circuit memory devices having a second memory organization to the interface such that the read data appears to have been read from the first plurality of integrated circuit memory devices having the first memory organization.
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Specification