DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD
First Claim
Patent Images
1. A data output control circuit of a semiconductor memory device for controlling data output in a read operation, comprising:
- a low frequency mode controller controlling a read command signal during a first operation mode to output the read command signal as a first command signal if the read command signal is determined to be a low frequency operation through a first CAS latency control signal;
a high frequency mode controller controlling the read command signal during a second operation mode to output the read command signal as a second command signal if the read command signal is determined to be a high frequency operation through a second CAS latency control signal; and
a selector selecting any one of the first and second command signals through CAS latency information to output one of the first and second command signals as a data output control signal.
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Abstract
A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.
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Citations
46 Claims
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1. A data output control circuit of a semiconductor memory device for controlling data output in a read operation, comprising:
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a low frequency mode controller controlling a read command signal during a first operation mode to output the read command signal as a first command signal if the read command signal is determined to be a low frequency operation through a first CAS latency control signal; a high frequency mode controller controlling the read command signal during a second operation mode to output the read command signal as a second command signal if the read command signal is determined to be a high frequency operation through a second CAS latency control signal; and a selector selecting any one of the first and second command signals through CAS latency information to output one of the first and second command signals as a data output control signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A data output control circuit of a semiconductor memory device for controlling a data output time point using a CAS latency and a DLL clock in a read operation, comprising:
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an operation mode controller providing a mode selection signal by which at least high and low frequencies can be discriminated in accordance with a frequency of the external clock signal through the CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies; a counter shifter counting and shifting an internal read command signal generated to perform the read operation by synchronizing it to the DLL clock in accordance with the state of the mode selection signal so as to be output as a first command signal; a delay unit delaying the internal read command signal by the pulse width of the pulse signal in accordance with the state of the mode selection signal so as to be output as a second command signal; and a selector selecting any one of the first and second command signals in accordance with the state of the mode selection signal so as to be output as a data output signal. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A data output control circuit, comprising:
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a read command generator generating a first internal read command signal through a read command signal generated in a read operation; a delay locked loop negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal; an operation mode controller providing a mode selection signal with which at least high and low frequencies can be discriminated in accordance with the frequency of the external clock signal through a CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies; a counter shifter counting and shifting the first internal read command signal by synchronizing it to the DLL clock in accordance with the state of the mode selection signal so as to be output as a second command signal; a delay unit delaying the first internal read command signal by the pulse width of the pulse signal in accordance with the state of the mode selection signal so as to be output as a third command signal; and a selector selecting any one of the second and third command signals in accordance with the state of the mode selection signal so as to be output as a data output signal. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A data output control circuit, comprising:
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a read command generator generating a first internal read command signal through a read command signal generated in a read operation; a delay locked loop negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal; an operation mode controller providing a mode selection signal with which at least high and low frequencies can be discriminated in accordance with the frequency of the external clock signal through a CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies; a delay unit counting the pulse signal to detect the pulse width of the pulse signal in accordance with the state of the mode selection signal, and then delaying the first internal read command signal by the pulse width of the pulse signal to be output as a second internal read command signal; a command selector selecting any one of the first and second internal read command signals in accordance with the state of the mode selection signal so as to be output as a third internal read command signal; and a data output controller counting and shifting the third internal read command signal by synchronizing it to the DLL clock in accordance with the state of the mode selection signal, or outputting an output signal of the delay detection mode unit (→
delay locked loop) as it is to be output as a data output control signal. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. A data output time point control method (→
- data output control method), comprising;
a first step of comparing first, second and third times to select a delay mode if it is determined to be a high frequency operation and to select a count shifting mode if it is determined to be a low frequency operation, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between an external clock signal and a DLL clock signal; a second step of detecting a fourth time in which the addition of the second and third times is subtracted from the first time and then delaying the internal read command signal by the fourth time to be output as a data output control signal for controlling a data output time point in a delay mode; and a third step of counting the internal read command signal through the DLL clock signal to be output as the data output control signal shifted by the fourth time in a count shifting mode. - View Dependent Claims (42, 43)
- data output control method), comprising;
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44. A data output control method, comprising:
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a first step of generating a first internal read command signal through a read command signal generated in a read operation; a second step of negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal; a third step of comparing first, second and third times to select a delay mode if it is determined to be a high frequency operation and to select a count shifting mode if it is determined to be a low frequency operation, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between the external clock signal and the DLL clock signal; a fourth step of outputting a pulse signal having a pulse width by a fourth time in which the addition of the second and third times is subtracted from the first time in the delay mode; a fifth step of counting the first delay pulse signal to detect the fourth time in the delay mode and then delaying the first internal read command signal by the fourth time to be output as a second internal read command signal; a sixth step of selecting the first internal read command signal in the count shifting mode, and selecting the second internal read command signal in the delay mode; and a seventh step of counting the first internal read command signal through the DLL clock signal to be output as a data output control signal for controlling a data output time point shifted by the fourth time in a count shifting mode, and outputting the second internal read command signal as the data output control signal as it is in the delay mode. - View Dependent Claims (45, 46)
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Specification