DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD

• US 20080080267A1
• Filed: 03/08/2007
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Hyeng Ouk
• Application Number:
  US11/683,490
• Publication Number:
  US 20080080267A1
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.

Claims

1. A data output control circuit of a semiconductor memory device for controlling data output in a read operation, comprising:

a low frequency mode controller controlling a read command signal during a first operation mode to output the read command signal as a first command signal if the read command signal is determined to be a low frequency operation through a first CAS latency control signal;

a high frequency mode controller controlling the read command signal during a second operation mode to output the read command signal as a second command signal if the read command signal is determined to be a high frequency operation through a second CAS latency control signal; and

a selector selecting any one of the first and second command signals through CAS latency information to output one of the first and second command signals as a data output control signal.

2. The data output control circuit as set forth in claim 1, wherein the first CAS latency control signal is a control signal for low frequencies, in which a CAS latency is bypassed, and the second CAS latency control signal is a control signal for high frequencies, generated by the CAS latency and data output delay information.

3. The data output control circuit as set forth in claim 2, wherein the low frequency mode controller counts and shifts the read command signal in accordance with the CAS latency to be output as the first command signal.

4. The data output control circuit as set forth in claim 2, wherein the high frequency mode controller delays the read command signal by a time in which a time corresponding to the data output delay is subtracted from the CAS latency so as to be output as the second command signal.

5. The data output control circuit as set forth in claim 4, wherein the high frequency mode controller delays the read command signal by a time in which an internal read command signal generation delay time is added to a time difference between external and DLL clock signals so as to be output as the second command signal after a read instruction.

6. The data output control circuit as set forth in claim 1, wherein the selector outputs the first command signal as the data output signal in a low frequency operation, and outputs the second command signal as the data output signal in a high frequency operation.

7. A data output control circuit of a semiconductor memory device for controlling a data output time point using a CAS latency and a DLL clock in a read operation, comprising:

an operation mode controller providing a mode selection signal by which at least high and low frequencies can be discriminated in accordance with a frequency of the external clock signal through the CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies;

a counter shifter counting and shifting an internal read command signal generated to perform the read operation by synchronizing it to the DLL clock in accordance with the state of the mode selection signal so as to be output as a first command signal;

a delay unit delaying the internal read command signal by the pulse width of the pulse signal in accordance with the state of the mode selection signal so as to be output as a second command signal; and

a selector selecting any one of the first and second command signals in accordance with the state of the mode selection signal so as to be output as a data output signal.

8. The data output control circuit as set forth in claim 7, wherein the operation mode controller compares first, second and third times so as to determine an operation mode depending on a frequency, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between the external clock signal and the DLL clock signal.

9. The data output control circuit as set forth in claim 8, wherein the operation mode controller includes:

a pulse generator generating a reference pulse signal with a pulse width that becomes a reference in discriminating high frequencies from low frequencies;

a first delay unit delaying the reference pulse signal by the first time through the CAS latency information and the external clock signal to be output as a first delay pulse signal;

a second delay unit delaying the reference pulse signal by a time in which the second and third times are added together to be output as a second delay pulse signal; and

a controller outputting the mode selection signal for comparing the first and second delay pulse signals to select an operation mode depending on a frequency and the pulse signal having a pulse width by a fourth time in which the addition of the second and third times is subtracted from the first time.

10. The data output control circuit as set forth in claim 9, wherein the controller outputs the mode selection signal denoting that the external clock signal is a high frequency if the first delay pulse signal is enabled when the second delay pulse is in an enable state, and outputs the mode selection signal denoting that the external clock signal is a low frequency if the first delay pulse signal is disabled when the second delay pulse is in an enable state.

11. The data output control circuit as set forth in claim 9, wherein the controller outputs a pulse signal having a pulse width by the fourth time that is enabled when the second delay pulse signal is enabled, and disabled when the first delay pulse is enabled.

12. The data output control circuit as set forth in claim 7, wherein the delay unit is operated when it is determined to be a high frequency by the state of the mode selection signal.

13. The data output control circuit as set forth in claim 12, wherein the delay unit includes:

a phase detector counting the pulse signal to detect the pulse width of the pulse signal when it is determined to be a high frequency by the state of the mode selection signal; and

a command delay unit delaying the internal read command signal in accordance with an output signal of the phase detector to be output as the second command signal.

14. The data output control circuit as set forth in claim 13, wherein the phase detector includes:

a plurality of first unit delay means connected in series to delay the pulse signal as a unit of a predetermined delay;

a detection means comparing the pulse signal with an output of each of the first unit delay means to be output as a detection signal enabled at a time point in which the pulse signal is is disabled; and

a selection means operated by the mode selection signal to output a delay selection signal for determining a delay degree of the internal read command signal through the detection signal.

15. The data output control circuit as set forth in claim 13, wherein the command delay unit includes:

a second unit delay means connected in series to delay the internal read command signal as a predetermined unit; and

a plurality of switching means each connected between an input/output node of each of the second unit delay means and a common node to be controlled by an output signal of the phase detector,

wherein the switching means corresponding to the output of the phase detector is turned on such that the second command signal is output to the common node.

16. The data output control circuit as set forth in claim 7, wherein the count shifter counts and shifts the internal read command signal through the CAS latency information and the DLL clock signal to be output as the first command signal when it is determined to be a low frequency by the state of the mode selection signal.

17. The data output control circuit as set forth in claim 16, wherein the count shifter is operated by the mode selection signal to count the internal read command signal by the CAS latency from which 1 is subtracted through the DLL clock signal.

18. A data output control circuit, comprising:

a read command generator generating a first internal read command signal through a read command signal generated in a read operation;

a delay locked loop negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal;

an operation mode controller providing a mode selection signal with which at least high and low frequencies can be discriminated in accordance with the frequency of the external clock signal through a CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies;

a counter shifter counting and shifting the first internal read command signal by synchronizing it to the DLL clock in accordance with the state of the mode selection signal so as to be output as a second command signal;

a delay unit delaying the first internal read command signal by the pulse width of the pulse signal in accordance with the state of the mode selection signal so as to be output as a third command signal; and

a selector selecting any one of the second and third command signals in accordance with the state of the mode selection signal so as to be output as a data output signal.

19. The data output control circuit as set forth in claim 18, wherein the operation mode controller compares first, second and third times so as to determine an operation mode depending on a frequency, the first time being a CAS latency count delay time, the second time being a first internal read command signal generation delay time after a read instruction and the third time being a time difference between the external clock signal and the DLL clock signal.

20. The data output control circuit as set forth in claim 19 wherein the operation mode controller includes:

a pulse generator generating a reference pulse signal with a pulse width that becomes a reference in discriminating high frequencies from low frequencies;

a first delay unit delaying the reference pulse signal by the first time through the CAS latency information and the external clock signal to be output as a first delay pulse signal;

a second delay unit delaying the reference pulse signal by a time in which the second and third times are added together to be output as a second delay pulse signal; and

a controller outputting the mode selection signal for comparing the first and second delay pulse signals to select an operation mode depending on a frequency and the pulse signal having a pulse width by a fourth time in which the addition of the second and third times is subtracted from the first time.

21. The data output control circuit as set forth in claim 20, wherein the controller outputs the mode selection signal denoting that the external clock signal is a high frequency if the first delay pulse signal is enabled when the second delay pulse is in an enable state, and outputs the mode selection signal denoting that the external clock signal is a low frequency if the first delay pulse signal is disabled when the second delay pulse is in an enable state.

22. The data output control circuit as set forth in claim 20, wherein the controller outputs a pulse signal having a pulse width by the fourth time that is enabled when the second delay pulse signal is enabled, and disabled when the first delay pulse is enabled.

23. The data output control circuit as set forth in claim 18, wherein the delay unit is operated when it is determined to be a high frequency by the state of the mode selection signal.

24. The data output control circuit as set forth in claim 23, wherein the delay unit includes:

a phase detector counting the pulse signal to detect the pulse width of the pulse signal when it is determined to be a high frequency by the state of the mode selection signal; and

a command delay unit delaying the first internal read command signal in accordance with an output signal of the phase detector to be output as the third internal read command signal.

25. The data output control circuit as set forth in claim 24, wherein the phase detector includes:

a plurality of first unit delay means connected in series to delay the pulse signal as a unit of a predetermined delay;

a detection means comparing the pulse signal with an output of each of the first unit delay means to be output as a detection signal enabled at a time point in which the pulse signal is is disabled; and

a selection means operated by the mode selection signal to output a delay selection signal for determining a delay degree of the first internal read command signal through the detection signal.

26. The data output control circuit as set forth in claim 24, wherein the command delay unit includes:

a second unit delay means connected in series to delay the first internal read command signal as a predetermined unit; and

a plurality of switching means each connected between an input/output node of each of the second unit delay means and a common node to be controlled by an output signal of the phase detector,

wherein the switching means corresponding to the output of the phase detector is turned on such that the third internal read command signal is output to the common node.

27. The data output control circuit as set forth in claim 18, wherein the count shifter counts and shifts the internal read command signal through the CAS latency information and the DLL clock signal to be output as the second internal read command signal when it is determined to be a low frequency by the state of the mode selection signal.

28. The data output control circuit as set forth in claim 27, wherein the count shifter is operated by the mode selection signal to count the internal read command signal by the CAS latency from which 1 is subtracted through the DLL clock signal.

29. A data output control circuit, comprising:

a read command generator generating a first internal read command signal through a read command signal generated in a read operation;

a delay locked loop negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal;

an operation mode controller providing a mode selection signal with which at least high and low frequencies can be discriminated in accordance with the frequency of the external clock signal through a CAS latency information and an external clock signal, and a pulse signal with a pulse width corresponding to a data output time point in high frequencies;

a delay unit counting the pulse signal to detect the pulse width of the pulse signal in accordance with the state of the mode selection signal, and then delaying the first internal read command signal by the pulse width of the pulse signal to be output as a second internal read command signal;

a command selector selecting any one of the first and second internal read command signals in accordance with the state of the mode selection signal so as to be output as a third internal read command signal; and

a data output controller counting and shifting the third internal read command signal by synchronizing it to the DLL clock in accordance with the state of the mode selection signal, or outputting an output signal of the delay detection mode unit (→

delay locked loop) as it is to be output as a data output control signal.

30. The data output control circuit as set forth in claim 29, wherein the operation mode controller compares first, second and third times so as to determine an operation mode depending on a frequency, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between the external clock signal and the DLL clock signal.

31. The data output control circuit as set forth in claim 30, wherein the operation mode controller includes:

a pulse generator generating a reference pulse signal with a pulse width that becomes a reference in discriminating high frequencies from low frequencies;

a first delay unit delaying the reference pulse signal by the first time to be output as a first delay pulse signal;

a second delay unit delaying the reference pulse signal by a time in which the second and third times are added together to be output as a second delay pulse signal; and

a controller outputting the mode selection signal for comparing the first and second delay pulse signals to select an operation mode depending on a frequency and the pulse signal having a pulse width by a fourth time in which the addition of the second and third times is subtracted from the first time.

32. The data output control circuit as set forth in claim 31, wherein the controller outputs the mode selection signal denoting that the external clock signal is a high frequency if the first delay pulse signal is enabled when the second delay pulse is in an enable state, and outputs the mode selection signal denoting that the external clock signal is a low frequency if the first delay pulse signal is disabled when the second delay pulse is in an enable state.

33. The data output control circuit as set forth in claim 31, wherein the controller outputs a pulse signal having a pulse width by the fourth time that is enabled when the second delay pulse signal is enabled, and disabled when the first delay pulse is enabled.

34. The data output control circuit as set forth in claim 29, wherein the delay unit is operated when it is determined to be a high frequency by the state of the mode selection signal.

35. The data output control circuit as set forth in claim 34, wherein the delay unit includes:

a phase detector counting the pulse signal to detect the pulse width of the pulse signal when it is determined to be a high frequency by the state of the mode selection signal; and

a command delay unit delaying the first internal read command signal in accordance with an output signal of the phase detector to be output as the second internal read command signal.

36. The data output control circuit as set forth in claim 35, wherein the phase detector includes:

a plurality of first unit delay means connected in series to delay the pulse signal as a unit of a predetermined delay;

a detection means comparing the pulse signal with an output of each of the first unit delay means to be output as a detection signal enabled at a time point in which the pulse signal is is disabled; and

a selection means operated by the mode selection signal to output a delay selection signal for determining a delay degree of the first internal read command signal through the detection signal.

37. The data output control circuit as set forth in claim 35, wherein the command delay unit includes:

a second unit delay means connected in series to delay the first internal read command signal as a predetermined unit; and

a plurality of switching means each connected between an input/output node of each of the second unit delay means and a common node to be controlled by an output signal of the phase detector,

wherein the switching means corresponding to the output of the phase detector is turned on such that the second internal read command signal is output to the common node.

38. The data output control circuit as set forth in claim 29, wherein the command selector includes:

an inverter inverting the mode selection signal;

a first NAND gate NAND combining the first internal read command signal and an output signal of the inverter;

a second NAND gate NAND combining the second internal read command signal and the mode selection signal; and

a third NAND gate NAND combining outputs of the first and second NAND gates to be output as the third internal read command signal.

39. The data output control circuit as set forth in claim 29, wherein the data output controller includes:

a count shifter counting and shifting the third internal read command signal through the CAS latency information and the DLL clock signal to be output as the data output control signal when it is determined to be a low frequency by the state of the mode selection signal; and

a transmission unit outputting the third internal read command signal as the data output control signal as it is when it is determined to be a high frequency by the state of the mode selection signal.

40. The data output control circuit as set forth in claim 39, wherein the count shifter is operated by the mode selection signal to count the internal read command signal by the CAS latency from which 1 is subtracted through the DLL clock signal.

41. A data output time point control method (→

data output control method), comprising;

a first step of comparing first, second and third times to select a delay mode if it is determined to be a high frequency operation and to select a count shifting mode if it is determined to be a low frequency operation, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between an external clock signal and a DLL clock signal;

a second step of detecting a fourth time in which the addition of the second and third times is subtracted from the first time and then delaying the internal read command signal by the fourth time to be output as a data output control signal for controlling a data output time point in a delay mode; and

a third step of counting the internal read command signal through the DLL clock signal to be output as the data output control signal shifted by the fourth time in a count shifting mode.

42. The data output control method as set forth in claim 41, wherein the first step includes the sub-steps of:

generating a reference pulse signal with a pulse width that becomes a reference in discriminating high frequencies from low frequencies;

delaying the reference pulse signal by the first time to be output as a first delay pulse signal;

delaying the reference pulse signal by a time in which the second and third times are added together to be output as a second delay pulse signal; and

comparing the first and second delay pulse signals to select the delay mode if the first delay pulse signal is enabled when the second delay pulse signal is in an enable state and to select the count shifting mode if the first delay pulse signal is disabled when the second delay pulse signal is in an enable state.

43. The data output control method as set forth in claim 41, wherein the second step includes the sub-steps of:

counting a signal having a pulse width by the fourth time to the fourth time; and

delaying the internal read command signal by the fourth time to be output as the data output control signal.

44. A data output control method, comprising:

a first step of generating a first internal read command signal through a read command signal generated in a read operation;

a second step of negative-delaying an external clock signal to be output as a DLL clock signal for the purpose of synchronizing read data to the external clock signal;

a third step of comparing first, second and third times to select a delay mode if it is determined to be a high frequency operation and to select a count shifting mode if it is determined to be a low frequency operation, the first time being a CAS latency count delay time, the second time being an internal read command signal generation delay time after a read instruction and the third time being a time difference between the external clock signal and the DLL clock signal;

a fourth step of outputting a pulse signal having a pulse width by a fourth time in which the addition of the second and third times is subtracted from the first time in the delay mode;

a fifth step of counting the first delay pulse signal to detect the fourth time in the delay mode and then delaying the first internal read command signal by the fourth time to be output as a second internal read command signal;

a sixth step of selecting the first internal read command signal in the count shifting mode, and selecting the second internal read command signal in the delay mode; and

a seventh step of counting the first internal read command signal through the DLL clock signal to be output as a data output control signal for controlling a data output time point shifted by the fourth time in a count shifting mode, and outputting the second internal read command signal as the data output control signal as it is in the delay mode.

45. The data output control method as set forth in claim 44, wherein the first step includes the sub-steps of:

generating a reference pulse signal with a pulse width that becomes a reference in discriminating high frequencies from low frequencies;

delaying the reference pulse signal by the first time to be output as a first delay pulse signal;

delaying the reference pulse signal by a time in which the second and third times are added together to be output as a second delay pulse signal; and

comparing the first and second delay pulse signals to select the delay mode if the first delay pulse signal is enabled when the second delay pulse signal is in an enable state and to select the count shifting mode if the first delay pulse signal is disabled when the second delay pulse signal is in an enable state.

46. The data output control method as set forth in claim 44, wherein the second step includes the sub-steps of:

counting a signal having a pulse width by the fourth time to the fourth time; and

delaying the internal read command signal by the fourth time to be output as the data output control signal.