Packet based ID generation for serially interconnected devices
First Claim
1. An apparatus comprising:
- a plurality of devices in a serial interconnection configuration, each device having a serial input connection (SI) for receiving serial input data and a serial output connection (SO) for providing serial output data,at least one of the devices having a packet based processing circuit for receiving a first packet containing a first ID (device identifier), generating a second ID as a function of the first ID and generating a second packet containing the second ID for transmission to another device in response to clocks such that there is a time gap between receiving the first packet and the transmission of the second packet.
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Abstract
Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
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Citations
29 Claims
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1. An apparatus comprising:
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a plurality of devices in a serial interconnection configuration, each device having a serial input connection (SI) for receiving serial input data and a serial output connection (SO) for providing serial output data, at least one of the devices having a packet based processing circuit for receiving a first packet containing a first ID (device identifier), generating a second ID as a function of the first ID and generating a second packet containing the second ID for transmission to another device in response to clocks such that there is a time gap between receiving the first packet and the transmission of the second packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for generating a device identifier (ID) in one of a plurality of devices in a serial interconnection configuration, each device having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the method comprising:
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receiving a first packet containing a first ID to be used as a device identifier; generating a second ID as a function of the first ID for another device; and sending a second packet containing the packet based ID for the other device, the first and second packets being non-overlapped in time. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A latency controller for use in an apparatus comprising a plurality of devices in a serial connected arrangement, each device having a serial input connection (SI) for receiving serial input data and a serial output connection (SO) for providing serial output data, at least one of the devices having a packet based processing circuit for receiving a first packet containing a first ID (device identifier) for the device, generating a second ID for another one of the devices and generating a second packet containing the second ID for transmission to the other device in response to clocks, the latency controller comprising:
a control circuit for controlling a clock latency in response to a received ID and the clock to provide a clock latency control signal, the clock latency control signal being used to ensure the first and second packets are non-overlapped in time.
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29. An ID producing apparatus for producing a device identifier (ID) coupled to one of a plurality of devices in a serial interconnection configuration, the one device having at least one cell for storing data, the one device having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the apparatus comprising:
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an input registration circuit for registering serial N-bit ID data contained in the serial input data and for providing the registered N-bit ID data as parallel N-bit ID data, N being an integer that is one or greater than one; a calculating circuit for performing a calculation based on the parallel N-bit ID data and given number data to provide N-bit calculation data as a generated device ID; a parallel-serial circuit for registering the N-bit calculation data as parallel N-bit calculated data and for providing the registered parallel N-bit calculated data as serial N-bit data, the serial N-bit data being forwarded to an input registering circuit included in another generating apparatus coupled to another device; and a transfer circuit for transferring the N-bit calculation data to the second device from the serial output connections of the first device to the serial input connections of the second device.
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Specification