Packet based ID generation for serially interconnected devices

• US 20080080492A1
• Filed: 09/29/2006
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom
• Granted Patent: US 8,700,818 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

Claims

1. An apparatus comprising:

a plurality of devices in a serial interconnection configuration, each device having a serial input connection (SI) for receiving serial input data and a serial output connection (SO) for providing serial output data,

at least one of the devices having a packet based processing circuit for receiving a first packet containing a first ID (device identifier), generating a second ID as a function of the first ID and generating a second packet containing the second ID for transmission to another device in response to clocks such that there is a time gap between receiving the first packet and the transmission of the second packet.

2. The apparatus of claim 1 wherein in respect of each device having a packet based processing circuit, the first ID is established as the ID of that device, and the second ID of is to be established as the ID of the other device.

3. The apparatus of claim 1 wherein in respect of each device having a packet based processing circuit, the second ID is established as the ID of the that device.

4. The apparatus of claim 1, wherein each device comprises:

an input/output data processing circuit for processing serial input data provided through the serial input connection, and providing serial output data to be sent through the serial output connection, the second packet being provided to the other device through the serial output connection for the at least one of the devices.

5. The apparatus of claim 4, wherein the input/output data processing circuit comprises:

an interpreter circuit for interpreting serial packet-based commands received at the serial input connection and for providing an interpreted ID as said first ID in response to the clock.

6. The apparatus of claim 5, wherein each device further comprises:

an ID generation circuit for performing a calculation based on the first ID to produce the second ID.

7. The apparatus of claim 6, wherein the ID generation circuit comprises:

a calculation circuit for adding a predetermined increment value to the first ID to provide the second ID.

8. The apparatus of claim 6, wherein the ID generation circuit comprises:

a calculation circuit for subtracting a predetermined decrement value to the first ID to provide the second ID.

9. The apparatus of claim 5, wherein the interpreter circuit comprises:

a serial packet interpreter for interpreting the serial packet-basis commands to provide interpreted packet commands and for further interpreting the interpreted packet commands to provide the interpreted ID.

10. The apparatus of claim 9, wherein the input/output data processing circuit further comprises:

a controller for controlling a clock latency in response to the interpreted ID and the clock to provide a clock latency control signal, the clock latency control signal controlling the output of the second packet such that there is a time gap between receiving the first packet and the transmission of the second packet.

11. The apparatus of claim 10, wherein the controller comprises:

a clock delay element (D-FFs) including a series-connected selectable time delay circuits; and

a selection circuit for selecting a combination of the selectable time delay circuits, in response to a latency control signal (CLC).

12. The apparatus of claim 11 wherein the controller further comprises:

at least one clock delay element that does not require selection and introduces a fixed delay.

13. The apparatus of claim 11, further comprising:

a control circuit for controlling operation of the serial interconnection of the devices, the control circuit providing the latency control signal to the selection circuit.

14. The apparatus of claim 11, wherein the input/output data processing circuit further comprises:

a packet output circuit for outputting an packet based ID in accordance with the new ID, in response to the clock latency control signal and the clock, the output packet based ID being provided to the serial output.

15. The apparatus of claim 14, wherein the device comprises a memory for storing data.

16. The apparatus of claim 15, wherein the memory includes a DRAM, a SRAM or flash memory.

17. The apparatus of claim 1 wherein each device further comprises an ID register for storing the first ID, thereafter the device being adapted to treat the first ID as the ID for the device.

18. The apparatus of claim 1, wherein the plurality of devices comprise first and second devices, the serial input connection of the first device being coupled to the serial output connection of a previous device, the serial input connection of the second device being coupled to the serial output connection of the first device:

the packet based processing circuit comprising;

an ID production circuit for producing the second device ID from signals received at the serial input connections of the first device in a packet basis; and

a transfer circuit for transferring the generated second device ID in a packet to the second device from the serial output connections of the first device to the serial input connections of the second device, packets containing IDs for two devices being non-overlapped in time.

19. A method for generating a device identifier (ID) in one of a plurality of devices in a serial interconnection configuration, each device having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the method comprising:

receiving a first packet containing a first ID to be used as a device identifier;

generating a second ID as a function of the first ID for another device; and

sending a second packet containing the packet based ID for the other device, the first and second packets being non-overlapped in time.

20. The method of claim 19 further comprising:

interpreting serial packet-basis commands received at the serial input to provide an interpreted ID as said first ID in response to a clock.

21. The method of claim 20, wherein the step of generating further comprises:

performing a calculation based on the interpreted ID to generate the second ID.

22. The method of claim 21, wherein the step of performing a calculation comprises:

adding a predetermined increment value to the interpreted ID to provide the second ID.

23. The method of claim 20, wherein the step of interpreting comprises:

interpreting the serial packet-basis commands to provide interpreted packet commands; and

further interpreting the interpreted packet commands to provide the interpreted ID.

24. The method of claim 20 further comprising:

controlling a clock latency in response to the interpreted ID and the clock to provide a clock latency control signal, so that the packets for two devices are non-overlapped in time.

25. The method of claim 19, wherein the plurality of devices comprise first and second devices, the serial input connection of the first device being coupled to the serial output connection of a previous device, the serial input connection of the second device being coupled to the serial output connection of the first device,

the step of receiving comprises receiving a command to write an ID in the first device in a first packet;

the step of generating comprises generating a device ID from signal received at the serial input connection of the first device in a packet basis in response to a clock; and

the step of sending comprises transferring the generated device ID to the second device from the serial output connection of the first device to the serial input connection of the second device in a second packet, the first and second packets being non-overlapped in time.

26. The method of claim 25, further comprising:

interpreting the received command to obtain the ID for the device;

controlling clock latency between interpreted serial input and the clock, so that the first and second packets are non-overlapped in time;

generating the device ID in response to the controlled clock latency and the new ID, the generated ID being provided through the serial output connection.

27. The method of claim 26, wherein the devices are in memory devices having memory portions for storing data that is accessed in a normal operation mode.

28. A latency controller for use in an apparatus comprising a plurality of devices in a serial connected arrangement, each device having a serial input connection (SI) for receiving serial input data and a serial output connection (SO) for providing serial output data, at least one of the devices having a packet based processing circuit for receiving a first packet containing a first ID (device identifier) for the device, generating a second ID for another one of the devices and generating a second packet containing the second ID for transmission to the other device in response to clocks, the latency controller comprising:

a control circuit for controlling a clock latency in response to a received ID and the clock to provide a clock latency control signal, the clock latency control signal being used to ensure the first and second packets are non-overlapped in time.

29. An ID producing apparatus for producing a device identifier (ID) coupled to one of a plurality of devices in a serial interconnection configuration, the one device having at least one cell for storing data, the one device having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the apparatus comprising:

an input registration circuit for registering serial N-bit ID data contained in the serial input data and for providing the registered N-bit ID data as parallel N-bit ID data, N being an integer that is one or greater than one;

a calculating circuit for performing a calculation based on the parallel N-bit ID data and given number data to provide N-bit calculation data as a generated device ID;

a parallel-serial circuit for registering the N-bit calculation data as parallel N-bit calculated data and for providing the registered parallel N-bit calculated data as serial N-bit data, the serial N-bit data being forwarded to an input registering circuit included in another generating apparatus coupled to another device; and

a transfer circuit for transferring the N-bit calculation data to the second device from the serial output connections of the first device to the serial input connections of the second device.