Method for leakage reduction in fabrication of high-density FRAM arrays

• US 20080081380A1
• Filed: 02/15/2007
• Published: 04/03/2008
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shinn, Gregory B., Udayakumar, Kezhakkedath R., Summerfelt, Scott R., Moise, Theodore S., Celii, Francis Gabriel
• Granted Patent: US 8,093,070 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Claims

1. A method of fabricating a ferroelectric capacitor structure in a semiconductor device, the method comprising:

forming a lower electrode diffusion barrier structure over a dielectric material, the lower electrode diffusion barrier layer at least partially engaging a conductive structure in the dielectric material;

forming a lower electrode over the lower electrode diffusion barrier structure;

forming a ferroelectric material over the lower electrode;

forming an upper electrode over the ferroelectric material;

forming a patterned etch mask over the upper electrode, the patterned etch mask exposing a portion of the upper electrode;

etching portions of the upper electrode, the ferroelectric material, and the lower electrode to define a patterned ferroelectric capacitor structure using the patterned etch mask;

etching a portion of the lower electrode diffusion barrier structure using the patterned etch mask;

ashing the patterned ferroelectric capacitor structure using a first ashing process comprising an oxygen/nitrogen/water-containing ash;

performing a wet clean process after the first ashing process; and

ashing the patterned ferroelectric capacitor structure using a second ashing process.

5. The method of claim 1, wherein the wet clean process comprises one or more of phosphoric acid, sulfuric acid and nitric acid.

7. The method of claim 1, wherein the second ashing process is performed at a temperature of about 325°

C. for a time of about 210 seconds.

8. The method of claim 7, wherein the second ashing process is performed at a power of about 1500 W and a pressure of about 1000 mT.

9. The method of claim 8, wherein the first ashing process, the wet clean process, and the second ashing process are performed after etching the portion of the lower electrode diffusion barrier structure and before an upper diffusion barrier or dielectric material is formed over the patterned ferroelectric capacitor structure.

10. The method of claim 1, further comprising forming an upper diffusion barrier or dielectric material over the patterned ferroelectric capacitor structure after the second ashing process.

2. (canceled)

3. (canceled)

4. The method of claim 3, wherein the first ashing process is performed at a power of about 1400 W and a pressure of about 2000 mT.

6. The method of claim 4 wherein the wet clean process comprises phosphoric acid at a concentration of about 50% and a temperature of about 65°

C.