Wafer level package structure of optical-electronic device and method for making the same

• US 20080081395A1
• Filed: 11/13/2007
• Published: 04/03/2008
• Est. Priority Date: 08/03/2004
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lu, Su-Tsai, Chen, Tai-Hung, Huang, Yuan-Chang, Lin, Yao-Sheng
• Granted Patent: US 7,465,603 B2
• Time in Patent Office: Days
• US Class Current: 438/64
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.

Claims

1. A wafer level package method for optical-electronic devices, comprising the steps of:

providing a substrate, whose surfaces have a plurality of optical sensitive areas and a plurality of bonding pads, the bonding pads providing electrical communications from each optical sensitive area to the exterior;

providing a transparent layer, whose surfaces have a plurality of conductive circuits, each of which corresponds a bonding pad on the substrate;

connecting the substrate surfaces to the transparent layer surfaces, so that the bonding pads are connected to the conductive circuits;

dividing the substrate into a plurality of chips, each contains at least one optical sensitive area and corresponding bonding pad;

forming a protection layer on each of the chips and exposing part of the conductive circuit;

forming a conductive film on the protection layer, so that the conductive film is connected to the exposed conductive circuit; and

dicing the transparent layer to form a chip level semiconductor package unit.

2. The wafer level package method for optical-electronic devices of claim 1, wherein the optical sensitive area is an optical sensitive device array.

3. The wafer level package method for optical-electronic devices of claim 1, wherein the bonding pad include a conductive bump.

4. The wafer level package method for optical-electronic devices of claim 1, wherein the conductive circuit includes a plurality of conductive bumps each of which corresponds to the connected bonding pad.

5. The wafer level package method for optical-electronic devices of claim 1 further comprising the step of thinning the substrate before the step of dividing the substrate into a plurality of chips.

6. The wafer level package method for optical-electronic devices of claim 1, wherein the step of forming a protection layer on transparent layer covering each of said chip includes the steps of coating a photo resist to form the protection layer, then separate said protection layer on each of said chip using photolithography method.

7-11. -11. (canceled)