Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same

• US 20080081398A1
• Filed: 10/02/2007
• Published: 04/03/2008
• Est. Priority Date: 10/02/2006
• Status: Abandoned Application

• Current Assignee: Phoco Co., Ltd.
• Original Assignee: Fionix Incorporated
• Inventors: Choi, Hyun-Jin, Lee, Sang-Hwan, An, Jae-Yong, Shin, Myoung-Seon, Ryu, Yeon-Duck
• Application Number:
  US11/866,277
• Publication Number:
  US 20080081398A1
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: B81B 2203/0384 sloped profile
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

The present invention relates to semiconductor device manufacturing techniques, and specifically to a field of device packaging techniques at wafer level. More specifically, it relates to a cap wafer for wafer bonding application that is bonded to top part of a device wafer. The method of the present invention excludes the use of deep reactive ion etching of silicon to form a through silicon via. The present invention provides a method for the preparation of cap wafer for wafer bonding application with a simple process of through silicon via interconnection and a wafer level packaging method using the same.

Claims

1. A method for preparing a cap wafer for wafer bonded packaging comprising the steps of:

i) forming an etch mask layer on Stop and back sides of a silicon wafer;

ii) selectively removing said etch mask layer to form a cavity etch window on the back side of said silicon wafer, and then forming a via etch window on the top side of said silicon wafer to overlap with said cavity etch window;

iii) forming a cavity and a via by wet etching of said silicon wafer that has been exposed by said cavity etch window and said via etch window, provided that a silicon diaphragm with a certain thickness is temporarily maintained between said cavity and said via;

iv) forming a cavity interconnection and a wafer bonding pad on the back side of said silicon wafer to which said cavity has been formed;

v) forming a through silicon via by removing the temporary silicon diaphragm under the bottom of said via so that the bottom of said via is in contact with the cavity interconnection;

vi) forming a via interconnection which contacts said cavity interconnection on the top side of said silicon wafer with said through silicon via formed thereon; and

vii) with a metallic bonding material, forming a device contact pad and a hermetic seal ring, respectively, on said cavity interconnection which is present on periphery of said cavity and on top of said wafer bonding pad.

2. The method for preparing a cap wafer for wafer bonding of claim 1, wherein the through silicon via is formed by dry or wet etching the entire top surface of said silicon wafer without etch mask.

3. The method for preparing a cap wafer for wafer bonding of claim 1, wherein the step of forming said through silicon via comprises the steps of:

i) forming a photoresist pattern over the top surface of said silicon wafer except the via region;

ii) further etching the remained silicon substrate under said via by dry etching method; and

iii) by mechanical polishing, removing the top surface of said silicon wafer to a certain depth where a negative profile of said via is present by under cut.

4. The method for preparing a cap wafer for wafer bonding of claim 1, wherein after the step of forming said cavity and via, the step of removing said etch mask layer remained on the top and back sides of said silicon wafer is more comprised.

5. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said silicon wafer has a 100 crystal plane, and said cavity etch window and said via etch window are aligned to be parallel with the 110 crystalline orientation.

6. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said etch mask layer is composed of one selected from silicon oxide layer, silicon nitride layer and stacked layer of silicon oxide layer/silicon nitride layer.

7. The method for preparing a cap wafer for wafer bonding of claim 4, wherein after the step of removing said etch mask layer remained on the top and back sides of said silicon wafer, the step of forming a dielectric layer on one or both surface of said silicon wafer is more comprised.

8. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said cavity interconnection, said wafer bonding pad and said via interconnection are respectively formed by a lift-off method.

9. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said cavity interconnection, said wafer bonding pad and said via interconnection are respectively formed by a selective metal etching method.

10. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said cavity interconnection, said wafer bonding pad and said via interconnection are respectively formed by plating additional metal film said cavity interconnection, said wafer bonding pad and said via interconnection.

11. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said cavity interconnection and said wafer bonding pad comprise the layers of:

i) a lowest layer which is at least one selected from Ti, Cr, TiN and TiW;

ii) a diffusion barrier layer which is at least one selected from Ni, Pt, Cu, Pd, TiN, TiW and TaN; and

iii) an uppermost layer of Au.

12. The method for preparing a cap wafer for wafer bonding of claim 1, wherein said metallic bonding material is composed of at least one selected from Au, Sn, In, Au—

Sn alloy, Sn—

Ag alloy, Au/Sn multi layer.

13. The method for preparing a cap wafer for wafer bonding of claim 12, wherein at the bottom of said metallic bonding material a diffusion barrier metal layer selected from Ni, Pt, Cr/Ni, Ti/Ni and Cr/Pt is more comprised.

14. Wafer bonded packaging method comprising the steps of:

i) forming an etch mask layer on top and back sides of a silicon wafer;

ii) patterning said etch mask layer to form a cavity etch window on the back side of silicon wafer, and then forming a via etch window on the top side of said silicon wafer to overlap with said cavity etch window;

iii) forming a cavity and a via by wet etching of said silicon wafer that has been exposed by said cavity etch window and said via etch window, provided that a silicon diaphragm with certain thickness is temporarily maintained between said cavity and said via;

iv) forming a cavity interconnection and a wafer bonding pad on the back side of said silicon wafer to which said cavity has been formed;

v) forming a through silicon via by removing the temporary silicon diaphragm under the bottom of said via in contact with the cavity interconnection;

vi) forming a via interconnection which contacts said cavity interconnection on the top side of said silicon wafer with said through silicon via formed thereon;

vii) with a metallic bonding material, forming a device contact pad and a hermetic seal ring, respectively on said cavity interconnection which is present on the periphery of said cavity and on top of said wafer bonding pad; and

viii) bonding the silicon cap wafer wherein said device contact pad and said hermetic seal ring have been formed to the device wafer wherein the device has been formed.

16. The method for preparing a cap wafer for wafer bonding of claim 14, wherein step of forming said through silicon via is provided by dry or wet etching of the entire top surface of said silicon wafer without an etch mask.

17. The method for preparing a cap wafer for wafer bonding of claim 14, wherein the step of forming said through via comprises the steps of:

i) forming a photoresist pattern over the top surface of said silicon wafer except the via region;

ii) further etching the remained silicon substrate under said via by a dry etching method; and

iii) by mechanical polishing, removing the top surface of said silicon wafer to a certain depth where a negative profile of said via is present by under cut.

18. The method for preparing a cap wafer for wafer bonding of claim 14, wherein said metallic bonding material is composed of at least one selected from Au, Sn, In, Au—

Sn alloy, Sn—

Ag alloy, Au/Sn multi layer.

15. A water bonded packaging method comprising the steps of:

i) forming an etch mask layer on top and back sides of a silicon wafer;

ii) selectively removing the said etch mask layer to form a cavity etch window on the back side of said silicon wafer, and then forming a via etch window on the top side of said silicon wafer to overlap with said cavity etch window;

iii) forming a cavity and a via by wet etching of said silicon wafer that has been exposed by said cavity etch window and said via etch window, provided that a silicon diaphragm with certain thickness is maintained between said cavity and said via;

iv) forming a cavity interconnection and a wafer bonding pad on the back side of said silicon wafer to which said cavity has been formed;

v) with a metallic bonding material, forming a device contact pad and a hermetic seal ring, respectively on said cavity interconnection which is present on the periphery of said cavity and on top of said wafer bonding pad;

vi) bonding the silicon cap wafer wherein said device contact pad and said hermetic seal ring have been formed to the device wafer wherein the device has been formed;

vii) forming a through silicon via by removing the temporary silicon diaphragm under the bottom of said via that the bottom of said via is in contact with the cavity interconnection; and

viii) forming a via interconnection which contacts said cavity interconnection on the top side of said silicon wafer with said through silicon via formed thereon.

19. The method for preparing a cap wafer for wafer bonding of claim 15, wherein step of forming said through silicon via is provided by dry or wet etching of the entire top surface of said silicon wafer without an etch mask.

20. The method for preparing a cap wafer for wafer bonding of claim 15, wherein the step of forming said through via comprises the steps of:

i) forming a photoresist pattern over the top surface of said silicon wafer except the via region;

ii) further etching the remained silicon substrate under neath of said via by a dry etching method; and

iii) by mechanical polishing, removing the top surface of said silicon wafer to a certain depth where a negative profile of said via is present by under cut.

21. The method for preparing a cap wafer for wafer bonding of claim 15, wherein said metallic bonding material is composed of at least one selected from Au, Sn, In, Au—

Sn alloy, Sn—

Ag alloy, Au/Sn multi layer.