On die thermal sensor

• US 20080082291A1
• Filed: 12/29/2006
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jeong, Chun-Seok, Park, Kee-Teok
• Granted Patent: US 7,965,571 B2
• Time in Patent Office: Days
• US Class Current: 702/136
• CPC Class Codes: G01K 7/015 using microstructures, e.g. made of silicon

Abstract

An on die thermal sensor (ODTS) for use in a semiconductor memory device includes: a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device in response to first and second enable signals and for generating a temperature information code which includes the sensed temperature information; and a flag signal logic determination unit for generating a plurality of first flag signals having temperature information and determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals.

Claims

1. An on die thermal sensor (ODTS) for use in a semiconductor memory device, comprising:

a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device in response to first and second enable signals and for generating a temperature information code including the sensed temperature information; and

a flag signal logic determination unit for generating a plurality of first flag signals having temperature information and for determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals.

2. The ODTS as recited in claim 1, wherein the flag signal logic determination unit includes:

a flag signal generation unit for generating a plurality of second flag signals whose logic levels are changed according to the temperature information code; and

a flag signal selection unit for selecting one of the plurality of second flag signals and a plurality of third flag signals to output the selected signal as the plurality of first flag signals in response to the first and second enable signals, the third flag signals having the predetermined logic level.

3. The ODTS as recited in claim 2, wherein the flag signal selection unit includes a multiplexer for receiving the plurality of second flag signals as a first input, the plurality of third flag signals as a second input and the first and second enable signals as a selection input, respectively, and selecting one of the second flag signals and the third flag signals in response to the first and second enable signals in order to output the selected signal as the first flag signals.

4. The ODTS as recited in claim 2, wherein the flag signal generation unit activates relatively large numbers of flag signals among the plurality of first flag signals when the temperature information code has relatively high internal temperature information of the semiconductor memory device.

5. The ODTS as recited in claim 2, wherein the flag signal generation unit activates relatively small numbers of flag signals among the plurality of first flag signals when the temperature information code has relatively low internal temperature information of the semiconductor memory device.

6. The ODTS as recited in claim 2, wherein the plurality of third flag signals have a constant logic level regardless of the temperature information code.

7. The ODTS as recited in claim 1, wherein the temperature information code generation unit is controlled in response to the first enable signal at a normal mode and is controlled in response to the first or second enable signal at a self refresh mode.

8. The ODTS as recited in claim 7, wherein the temperature information code generation unit is disabled from operation at the normal mode and the self refresh mode when the first and second enable signals are inactivated.

9. The ODTS as recited in claim 7, wherein the temperature information code generation unit is disabled from operation at the normal mode and is enabled to be operated at the self refresh mode when the first enable signal is inactivated and the second enable signal is activated.

10. The ODTS as recited in claim 7, wherein the temperature information code generation unit is enabled to be operated regardless of the second enable signal when the first enable signal is activated.

11. The ODTS as recited in claim 1, wherein the temperature information code generation unit includes:

a temperature sensing unit for generating a temperature voltage, a first variation reference voltage and a second variation reference voltage, wherein the temperature voltage has minus (−

) characteristics toward an increase of temperature and the first and the second variation reference voltages have a constant voltage level regardless of temperature variation; and

an analog-digital converting unit for generating the temperature information code by converting the temperature voltage, which is an analog value, to the temperature information code, which is a digital value, according to each voltage level of the first and the second variation reference voltages.

12. The ODTS as recited in claim 11, wherein the temperature information code generation unit further includes a multipurpose register for receiving and storing the temperature information code.

13. The ODTS as recited in claim 11, wherein the analog-digital converting unit includes:

a comparison unit for comparing the temperature voltage with a tracking voltage in order to increase or decrease the temperature information code based on the comparison result; and

a voltage level determination unit for determining a voltage level of the tracking voltage in response to the temperature information code, wherein the voltage level of the tracking voltage is smaller than or equal to the first variation reference voltage and is larger than or equal to the second variation reference voltage.

14. The ODTS as recited in claim 13, wherein the comparison unit includes:

a comparator for comparing the temperature voltage with the tracking voltage in response to a clock signal received from a memory controller in order to determine each logic level of an increase signal and a decrease signal according to the comparison result; and

an up/down counter for increasing and decreasing the temperature information code in response to the increase signal and the decrease signal, wherein the up/down counter is operated in response to a delayed clock which is generated by delaying the clock signal.

15. The ODTS as recited in claim 14, wherein the comparison unit further includes a filtering unit for filtering the increase signal and the decrease signal in order to prevent the up/down counter from being incorrectly operated.

16. The ODTS as recited in claim 13, wherein the voltage level determination unit includes a digital-analog converter for converting the temperature information code to the tracking voltage, wherein a voltage level of the tracking voltage is changed in response to the first and the second variation reference voltages.

17. The ODTS as recited in claim 16, wherein the voltage level determination unit further includes a decoder for decoding the temperature information code and for transferring the decoded signal to the digital-analog converter in order to prevent the digital-analog converter from being incorrectly operated.

18. A semiconductor memory device, comprising:

a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device at an on state in response to first and second enable signals and generating a temperature information code including the sensed temperature information;

a flag signal logic determination unit for generating a plurality of first flag signals having temperature information, and determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals; and

a self refresh period change unit for changing a period of a self refresh operation at a self refresh mode in response to the plurality of first flag signals.

19. The semiconductor memory device as recited in claim 18, wherein the flag signal logic determination unit includes:

a flag signal generation unit for generating a plurality of second flag signals whose logic levels are changed according to the temperature information code; and

a flag signal selection unit for selecting one of the plurality of second flag signals and a plurality of third flag signals to output the selected signal as the plurality of first flag signals in response to the first and second enable signals, the third flag signals having the predetermined logic level.

20. The semiconductor memory device as recited in claim 19, wherein the flag signal selection unit includes a multiplexer for receiving the plurality of second flag signals as a first input, the plurality of third flag signals as a second input and the first and second enable signals as a selection input, respectively, and selecting one of the second flag signals and the third flag signals in response to the first and second enable signals in order to output the selected signal as the first flag signals.

21. The semiconductor memory device as recited in claim 18, wherein the flag signal logic determination unit activates relatively large numbers of flag signals among the plurality of first flag signals when the temperature information code has relatively high internal temperature information of the semiconductor memory device.

22. The semiconductor memory device as recited in claim 21, wherein the self refresh period change unit decreases the period of the self refresh operation when relatively large numbers of flag signals among the plurality of first flag signals are activated.

23. The semiconductor memory device as recited in claim 18, wherein the flag signal logic determination unit activates relatively small numbers of flag signals among the plurality of first flag signals when the temperature information code has relatively low internal temperature information of the semiconductor memory device.

24. The semiconductor memory device as recited in claim 23, wherein the self refresh period change unit increases the period of the self refresh operation when relatively small numbers of flag signals among the plurality of first flag signals are activated.

25. The semiconductor memory device as recited in claim 19, wherein the plurality of third flag signals have a constant logic level regardless of the temperature information code.