Memory Cards with End of Life Recovery and Resizing

• US 20080082726A1
• Filed: 09/28/2006
• Published: 04/03/2008
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Elhamias, Reuven
• Granted Patent: US 7,596,656 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation

Abstract

A system and methods are given for providing information on the amount of life remaining for a memory having a limited lifespan, such as a flash memory card. For example, it can provide a user with the amount of the memory'"'"'s expected remaining lifetime in real time units or as a percentage of estimated initial life. An end of life warning can also be provided. The memory device can be resized by host command. In an exemplary embodiment, a host can send a request to the memory device obtain its status and the size of logical units with which it operates. Based on this information, portions of the memory device can be erased, after which it can be reformatted and operated with a reduce capacity.

Claims

1. A system including:

a host; and

a memory device in communication with the host, the memory device comprising;

a memory having a plurality of physical memory segments each having a plurality of non-volatile memory cells and organized into logical units; and

a controller, wherein the controller logically accesses the memory as having a first accessible physical memory capacity and, in response to a command from the host, subsequently logically accesses the memory as having a second accessible physical memory capacity, where the second accessible physical memory capacity is less than the first accessible physical memory capacity.

2. The system of claim 1, the memory further including:

erase circuitry attachable to the memory cells wherein, in response to said command from the host, the memory device erases a number of logical units of said non-volatile memory.

3. The system of claim 2, wherein the controller operates the memory device according to a protocol and, in response to said command, the controller updates the protocol by which the memory device operates.

4. The system of claim 3, the memory including one or more registers, wherein updating the protocol includes resetting one or more register values from which the host can determine the capacity of the memory device.

5. The system of claim 3, wherein updating the protocol includes changing the number of physical memory segments into which the controller organizes each of said logical units.

6. The system of claim 3, wherein subsequent to completing said erase of a number of logical units of said non-volatile memory, the controller sends an indication that the erasing is complete to the host prior to the host accessing the memory device as having the second accessible physical memory capacity.

7. The system of claim 2, wherein said command supplies the number of logical units of said non-volatile memory to erase.

8. The system of claim 7, wherein the host calculates said number based on the number of physical memory segments composing a logical unit.

9. The system of claim 8, wherein the physical memory segment is the physical unit of erase.

10. The system of claim 8, wherein number of physical memory segments composing a logical unit is supplied from the memory device to the host in response to a command from the host.

11. The system of claim 10, wherein said number of physical memory segments composing a logical unit is supplied in terms of the number of sectors.

12. The system of claim 1, wherein the host reformats the memory device prior to accessing the memory device as having the second accessible physical memory capacity.

13. The system of claim 1, wherein the memory cells each have a lifetime of a finite number rewrite cycles, the memory further including:

rewrite circuitry connectable to said memory cells whereby the memory cells can be rewritten, and

wherein the controller maintains a parameter indicative of the number of rewrites the memory cells have undergone, determines an indication of the expected amount of remaining lifetime of the memory system based on the value of said parameter, and provides said indication of the expected amount of remaining lifetime to the host, and

wherein said command from the host to the memory device to reduce the accessible physical memory capacity is in response to said indication of the expected amount of remaining lifetime of the memory device.

14. The system of claim 13, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to a status request from the host.

15. The system of claim 13, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to the expected amount of remaining lifetime being less than a predetermined value.

16. The system of claim 13, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to the memory device transitioning to a read only mode.

17. The system of claim 13, wherein said indication of the expected amount of remaining lifetime of the memory device includes a number of logical units to erase.

18. The system of claim 1, wherein the host backs-up data stored on the memory device prior to sending said command.

19. The system of claim 1, wherein the memory system is detachably connected to the host.

20. The system of claim 1, wherein the memory system is embedded in the host.

21. The method of claim 1, wherein the memory system includes a wireless interface through which it is in communication with the host.

22. A memory device, comprising:

a memory having a plurality of physical memory segments each having a plurality of non-volatile memory cells and organized into logical units; and

a controller, wherein the controller logically accesses the memory as having a first accessible physical memory capacity and, in response to a command from a host to which the memory device is connected, subsequently logically accesses the memory as having a second accessible physical memory capacity, where the second accessible physical memory capacity is less than the first accessible physical memory capacity.

23. The memory device of claim 22, the memory further including:

erase circuitry attachable to the memory cells wherein, in response to said command from the host, the memory device erases a number of logical units of said non-volatile memory.

24. The memory device of claim 23, wherein the controller operates the memory device according to a protocol and, in response to said command, the controller updates the protocol by which the memory device operates.

26. The memory device of claim 24, wherein updating the protocol includes changing the number of physical memory segments into which the controller organizes each of said logical units.

27. The memory device of claim 24, wherein subsequent to completing said erase of a number of logical units of said non-volatile memory, the controller sends an indication that the erasing is complete to the host.

28. The memory device of claim 23, wherein said command supplies the number of logical units of said non-volatile memory to erase.

29. The system of claim 22, wherein the memory cells each have a lifetime of a finite number rewrite cycles, the memory device further including:

rewrite circuitry connectable to said memory cells whereby the memory cells can be rewritten, and

wherein the controller maintains a parameter indicative of the number of rewrites the memory cells have undergone, determines an indication of the expected amount of remaining lifetime of the memory system based on the value of said parameter, and provides said indication of the expected amount of remaining lifetime to the host, and

wherein said command from the host to the memory device to reduce the accessible physical memory capacity is in response to said indication of the expected amount of remaining lifetime of the memory device.

30. The memory device of claim 29, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to a status request from the host.

31. The memory device of claim 29, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to the expected amount of remaining lifetime being less than a predetermined value.

32. The memory device of claim 29, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the host in response to the memory device transitioning to a read only mode.

33. The memory device of claim 29, wherein said indication of the expected amount of remaining lifetime of the memory device includes a number of logical units to erase.

34. The memory device of claim 22, wherein the memory system is detachably connectable to the host.

35. The memory device of claim 22, wherein the memory system is embedded in the host.

36. The memory device of claim 22, wherein the memory system further includes a wireless interface through which it is in communication with said host.

25. The memory device 24, the memory device including one or more registers, wherein updating the protocol includes resetting one or more register values from which the host can determine the capacity of the memory device.

37. A digital appliance, comprising:

an interface for placing the digital appliance in communication with a memory device having a non-volatile memory for the exchange of data and commands therethrough; and

logic circuitry for accessing the memory device through the interface, wherein the commands include a resize command and where the digital appliance accesses the memory device according to a file system as having a first accessible physical memory capacity and, subsequent to sending the resize command to the memory device to reduce the accessible physical memory capacity from said first accessible physical memory capacity to a second accessible physical memory capacity and receiving an indication from the memory device of completing the resizing, the logic circuitry updates the file system according to the resizing prior to subsequently accessing the memory device according to the updated file system.

38. The digital appliance of claim 37, wherein the logic circuitry sends said resizing command to the memory device is in response to an indication of the expected amount of remaining lifetime of the memory device.

39. The digital appliance of claim 38, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the digital appliance in response to a status request from the digital appliance.

40. The digital appliance of claim 38, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the digital appliance in response to the expected amount of remaining lifetime being less than a predetermined value.

41. The digital appliance of claim 38, wherein said indication of the expected amount of remaining lifetime of the memory device is provided from the memory device to the digital appliance in response to the memory device transitioning to a read only mode.

42. The digital appliance of claim 37, wherein the digital appliance backs up stored on the memory device prior sending said resizing command.

43. The digital appliance of claim 37, wherein the interface includes a detachable connector whereby the memory system is detachably connected to the digital appliance.

44. The digital appliance of claim 37, wherein the memory system is embedded in the digital appliance.

45. The digital appliance of claim 37, wherein the interface is a wireless interface.