Multi-chip flash memory device and copy-back method thereof

• US 20080082730A1
• Filed: 12/28/2006
• Published: 04/03/2008
• Est. Priority Date: 10/03/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, In-Young, Choi, Young-Joon, Kim, Jong-Hwa, Kim, Soon-Young
• Granted Patent: US 7,865,657 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

A method and device for copying-back data in a multi-chip flash memory device having first and second memory chips. The method may include reading first source data from a first source region of one of the memory chips; programming the first source data into a target region included in one of the memory chips and reading second source data from second source region of the other memory chip different from the memory chip including the target region. Reading the second source data may be carried out while programming the first source data.

Claims

1. A method of copying-back data in a multi-chip flash memory device having first and second memory chips, comprising:

reading first source data from a first source region of one of the memory chips;

programming the first source data into a target region included in one of the memory chips; and

reading second source data from second source region of the other memory chip different from the memory chip including the target region,

wherein reading the second source data is carried out while programming the first source data.

2. The method as set forth in claim 1, wherein when the first source region and the target region are included in the first memory chip, the second source region is included in the second memory chip.

3. The method as set forth in claim 2, wherein reading the second source data includes detecting whether the first source data have been programmed into the target region.

4. The method as set forth in claim 1, wherein when the first source region is included in the first memory chip and the target region is included in the second memory chip, the second source region is included in the first memory chip.

5. The method as set forth in claim 4, wherein reading the second source data includes detecting whether the first source data have been programmed into the target region.

6. The method as set forth in claim 1, wherein the first and second source regions and the target region are correspondent each with data storage regions each of which is a unit of page.

7. The method as set forth in claim 1, further comprising:

correcting errors of the first and second source data read out.

8. The method as set forth in claim 1, wherein the first and second memory chips are NAND flash memory devices.

9. A multi-chip flash memory device comprising:

a first memory chip;

a second memory chip; and

a memory controller programming a target region of one of the first and second memory chips with first source data read out from the first memory chip during a copy-back operation, and regulating the first and second memory chips to read second source data from a second source region of the other memory chip different from the memory chip including the target region during a period of the programming.

10. The multi-chip flash memory device as set forth in claim 9, wherein the first and second memory chips share a chip selection signal.

11. The multi-chip flash memory device as set forth in claim 10, wherein the first and second memory chips are alternatively selected in accordance with a level of the chip selection signal.

12. The multi-chip flash memory device as set forth in claim 9, wherein the memory controller executes an error correction operation for the first and second source data.

13. A multi-chip flash memory device comprising:

an input/output bus;

a first memory chip, during programming, providing status data, which reports completion status of the programming in response to a status detection command and a read enable signal;

a second memory chip, during programming, conducting a read to output read data to the input/output bus, before outputting the status data, in response to a read command and interrupting a data output to the input/output bus at an output time of the status data; and

a memory controller providing the first and second memory chips with the status detection command, the read command, and an address via the input/output bus and conducting a copy-back operation in accordance with the programming and reading.

14. The multi-chip flash memory device as set forth in claim 13, wherein the first and second memory chips share a chip selection signal, a write enable signal, and a read enable signal which are provided from the memory controller.

15. The multi-chip flash memory device as set forth in claim 14, wherein the first and second memory chips are alternatively selected in accordance with a level of the chip selection signal.

16. The multi-chip flash memory device as set forth in claim 13, wherein the first memory chip includes:

a first cell array;

a first input/output buffer storing the status data; and

a first control logic block conducting the programming for the first cell array in response to an address, a write enable signal, and a read enable signal and regulating to output the status data in response to the status detection command.

17. The multi-chip flash memory device as set forth in claim 16, wherein the first control logic block includes a first buffer controller activating an output of the first input/output buffer in response to the status detection command and the address.

18. The multi-chip flash memory device as set forth in claim 13, wherein the second memory chip includes:

a second cell array;

a second input/output buffer storing the read data; and

a second control logic block conducting the reading for the second cell array in response to an address, a write enable signal, and a read enable signal and regulating an output of the second input/output buffer in response to the status detection command.

19. The multi-chip flash memory device as set forth in claim 18, wherein the second control logic block includes a second buffer controller interrupting the output of the second input/output buffer in response to the status detection command.