APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF

• US 20080082763A1
• Filed: 10/02/2006
• Published: 04/03/2008
• Est. Priority Date: 10/02/2006
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Rajan, Suresh Natarajan
• Application Number:
  US11/538,041
• Publication Number:
  US 20080082763A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Claims

1. A method, comprising:

communicating with a plurality of physical memory circuits; and

simulating at least one virtual memory circuit with at least one power-related aspect that is different from at least one aspect of at least one of the physical memory circuits.

2. The memory of claim 1, wherein the simulating is performed by an interface circuit.

3. The method of claim 2, wherein the interface circuit is selected from the group consisting of a buffer, a register, an advanced memory buffer (AMB), and a component positioned on at least one dual in-line memory module (DIMM).

4. The method of claim 3, wherein the interface circuit includes the buffer and is selected from the group consisting of a buffer chip, a data register chip, a multiplexer/de-multiplexer chip, and a synchronous multiplexer/de-multiplexer chip.

5. The method of claim 3, wherein the interface circuit includes the register and is selected from the group consisting of an address register chip, a control register chip, and an address/control register chip.

6. The method of claim 1, wherein the simulating is performed by a component of a system.

7. The method of claim 6, wherein the component of the system includes a memory controller.

8. The method of claim 1, wherein the at least one power-related aspect includes a timing.

9. The method of claim 1, wherein the at least one power-related aspect includes a relative period of a first state of the physical memory circuits with respect to a period of a second state of the physical memory circuits.

10. The method of claim 9, wherein the first state is a precharge state.

11. The method of claim 9, wherein the second state is an active state.

12. The method of claim 1, wherein the at least one power-related aspect includes power behavior.

13. The method of claim 12, wherein the at least one power-related aspect includes a number of power management signals.

14. The method of claim 12, wherein the at least one power-related aspect includes a type of power management signals.

15. The method of claim 14, wherein the type of power management signals is selected from the group consisting of a time-multiplexed power management signal, a bussed power management signal, an encoded power management signal, and a unencoded power management signal.

16. The method of claim 12, wherein the at least one power-related aspect includes a placement of power management signals.

17. The method of claim 16, wherein the placement of power management signals includes placement of power management signals in at least one of an address field, a data field, at least one unused pin on a dual in-line memory module (DIMM), a clock enable signal, and a chip select signal.

18. An apparatus, comprising:

a component of a system in communication with a plurality of physical memory circuits, the component of the system operable to communicate with the physical memory circuits and simulate at least one virtual memory circuit with at least one aspect that is different from at least one aspect of at least one of the physical memory circuits.

19. The apparatus of claim 18, wherein the component of the system includes a memory controller.

20. The apparatus of claim 18, wherein the component of the system works in combination with an interface circuit for simulating the at least one aspect.

21. The apparatus of claim 20, wherein the interface circuit interfaces at least one of data signals and address signals.

22. The apparatus of claim 20, wherein the component of the system simulates the at least one aspect utilizing a latency of the physical memory circuits.

23. The apparatus of claim 18, wherein the at least one aspect includes a power-related aspect.

24. The apparatus of claim 23, wherein the at least one power-related aspect includes power management of an interface circuit.

25. The apparatus of claim 23, wherein the at least one power-related aspect includes power management of at least one of a receiver circuit and a driver circuit of the interface circuit.

26. The apparatus of claim 23, wherein the at least one power-related aspect is simulated by adjusting a parameter selected from the group consisting of a tFAW parameter, a tRRD parameter, a tRP parameter, a tRFC(min) parameter, and a tRCD parameter.

27. The apparatus of claim 23, wherein the at least one power-related aspect is simulated by switching between 1T and 2T modes.

30. The method of claim 19, wherein the second number of portions includes a single portion.

28. A method, comprising:

communicating with at least one physical memory circuit having a first number of portions; and

simulating at least one virtual memory circuit having a second number of portions that is different from the first number of portions of the at least one physical memory circuit.

29. The method of claim 28, wherein the second number is less than the first number.

31. The method of claim 28, wherein the simulating results in a power savings.

32. A system, comprising:

at least one physical memory circuit having a first number of portions; and

means for simulating at least one virtual memory circuit having a second number of portions that is different from the first number of portions of the at least one physical memory circuit.

33. A method, comprising:

communicating with a plurality of physical memory circuits; and

simulating at least one virtual memory circuit with at least one aspect that is different from at least one aspect of at least one of the physical memory circuits;

wherein the at least aspect is selected from the group consisting of a signal, a portion, a partition, an organization, a mapping, a timing, and a latency.