Super-scalable, continuous flow instant logic™ binary circuitry actively structured by code-generated pass transistor interconnects

• US 20080082786A1
• Filed: 10/02/2006
• Published: 04/03/2008
• Est. Priority Date: 10/02/2006
• Status: Active Grant

• Current Assignee: WEND LLC
• Original Assignee: WEND LLC
• Inventors: Lovell, William Stuart
• Granted Patent: US 7,895,560 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16

Abstract

A processing space contains an array of operational transistors interconnected by circuit and signal pass transistors that when supplied with selected enable bits will structure a variety of circuits that will carry out any desired information processing. The Babbage/von Neumann Paradigm in which data are provided to circuitry that would operate on those data is reversed by structuring the desired circuits at the site(s) of the data, thereby to eliminate the von Neumann bottleneck and substantially increase the computing power of the device, with the apparatus conducting only non-stop Information Processing on a steady stream of data and code, with no repetitious Instruction and data transfers as in the normal computer being required. A code is defined that will identify the physical locations of every transistor in the processing space, which code will then enable only selected ones of the pass transistors therein so as to structure the circuits needed for any algorithm sought to be executed. The circuits so structured, operating independently of and in parallel with every other circuit so structured, are then restructured after each step into another group of circuits, so that almost no transistor will ever “sit idle,” but all of the processing space can be devoted entirely to information processing, thereby again to increase enormously the computing power of the device. The apparatus is also super-scalable, meaning that an Instant Logic Apparatus built around that processing space could be built to have any size, speed, and level of computer power desired.

Claims

1. A method for achieving super-scalability in an information processing apparatus that is to be installed in a processing space, comprising:

Providing a multiplicity of functionally inter-connectable information processing modules that each comprise all of the data-relevant circuitry needed to carry out desired information processing operations, wherein each of said information processing modules further comprises a multiplicity of processing elements, each of said processing elements further comprising a pre-determined number of contact terminals to which connection can be made in the number of directions as may be defined by the dimensionality of the processing space within which said information processing modules are to be installed; and

Interconnecting a number of said information processing modules to at least one other information processing module in a geometrical pattern having a periphery, such that as new information processing modules are added, the ratio of said information processing modules that lie on said periphery of the geometric pattern so obtained to the total number of said information processing modules will decrease;

Whereby, since as to information processing modules that lie on said periphery will face at least one direction where there will be no other information processing module to which connection could be made, said information processing module then not being fully usable, the ratio of the number of said processing elements that are not fully usable to the total number of said information processing modules will likewise decrease.

2. A method of information processing wherein instead of transporting instructions and data to a site at which circuitry is present that is capable of carrying out desired information processing of data that that are received by said circuitry, structuring said circuitry that is capable of carrying out said desired information processing of said data that are received by said circuitry at those sites at which said data are located or are expected to appear.

3. The method of information processing of claim 2 based on eliminating the “

von Neumann bottleneck,”

wherein data requiring information processing and the instructions that would bring about that processing are transferred from memory to circuitry that would carry out said information processing, with said instructions, and said data in the form resulting from that information processing, then being returned to memory and another round of fetching instructions and data then being begun, said method based on eliminating the “

von Neumann bottleneck”

comprising instead the following steps;

Providing an array of passive energy transmission circuits that can be structured into active energy transmission circuits;

Identifying one or more passive energy transmission circuit locations within said array of passive energy transmission circuits at which data requiring information processing are to appear;

Structuring from said one or more passive energy transmission circuits the types of active energy transmission circuits that are appropriate to the kinds of information processing desired, including input terminals thereto, at such locations within said array of passive energy transmission circuits as will place said input terminals of said active energy transmission circuits that are being structured at locations relative to said locations at which data requiring information processing are to appear that will allow entry of said data requiring information processing into said input terminals of said active energy transmission circuits that had been so structured, whereby any streams of said data as may be caused to enter into various ones of said array of what had been passive energy transmission circuits will instead encounter said active energy transmission circuits that were structured so as to carry out the kinds of information processing desired, and said information processing will commence upon the appearance of said data requiring information processing; and

Repeating said structuring of active energy transmission circuits with respect both to data that were newly created in executing each preceding step of information processing and to data that were yet entering said array of originally passive energy transmission circuits as parts of said streams of data.

4. Apparatus for information processing, comprising:

An array of passive energy transmitting devices, each having a number of connectible terminals thereon and being disposed along directions as defined by the dimensionality of said array, each of said passive energy transmitting devices being capable of being transformed into a corresponding active energy transmitting device capable of receiving energy packets having information contained therein and performing information processing on said energy packets, wherein certain identified ones of said passive energy transmitting devices await the entry therein of said energy packets;

An array of active energy transmitting devices having proximal and distal ends, said active energy transmitting devices being capable of passing energy packets therethrough upon the imposition thereto of an enabling signal, with said proximal ends of said active energy transmitting devices being connected respectively to different ones of said connectible terminals on said passive energy transmitting devices, and said distal ends of said active energy transmitting devices being connected respectively to

An energy source, an entry location for energy packets, an energy sink, and to said set of connectible terminals as are disposed on at least one other of said passive energy transmitting devices; and

Addressing means by which enabling signals can be directed to selected ones of said passive energy transmitting devices;

whereupon

The imposition of an enabling signal onto one or more of said active energy transmitting devices connected to one or more of said passive energy transmitting devices that await the entry therein of said energy packets will transform said one or more passive energy transmitting devices into corresponding active energy transmitting devices that are capable of performing information processing upon the entry of energy packets into said entry location for energy packets.

5. The apparatus of claim 4 wherein said apparatus, said passive energy transmission devices and said active energy transmission devices are electronic circuits, said energy is electronic energy, and said enabling signal is an enabling voltage.

6. The electronic circuit of claim 5 wherein said electronic circuits as to said passive energy transmission circuits comprise operational transistors and as to said active energy transmission circuits comprise pass transistors, said energy packets are electronic bits, and said array of operational transistors and pass transistors comprises a processing space,

7. The electronic circuit of claim 6 wherein said application of enabling voltages to said pass transistors is controlled by code entered into said processing space through a code selector unit.

8. The electronic circuit of claim 7 wherein said code selector unit comprises a circuit code selector and a signal code selector.

9. The electronic circuit of claim 8 wherein said circuit code selector comprises:

A number of circuit code input nodes each being connected respectively to a first input to an XNOR gate;

said XNOR gates being equal in number to the number of said circuit code input nodes;

Reference latches holding the respective values “

0” and

“

1”

that connect respectively to a second input to each of said XNOR gates, whereupon the entry of the same bit value from said circuit code input node to said first input to said XNOR gate as the bit value of said code reference latch that is connected to the second input to said XNOR gate will bring about a “

1”

bit output from said XNOR gate;

wherein

The said “

0” and

“

1”

bit values that are held in said reference latches are established in such a manner as to form a number of bit combinations of a pre-selected bit length, each of said bit combination being distinct in terms of the bit values held from every other bit combination formed in that same manner;

Each of said distinct bit combination is connected to said second inputs of a particular one of a number of arrays of XNOR gates wherein the bit length of each said array of XNOR gates is the same as the bit lengths of said distinct bit combinations,

Each XNOR gate of a particular said array of XNOR gates to which any one of said bit combinations is sent from said reference latches is a different XNOR gate from any XNOR gate to which a different one of said bit combinations has been sent;

A number of AND gates each having a number of inputs equal to the number of XNOR gates contained in each of said arrays of said XNOR gates, the output of each of said XNOR gates of a particular array of said XNOR gates being connected respectively to each of said inputs to that one of said AND gates to which are connected the outputs of those said XNOR gates that are connected to the particular AND gate, whereby

Upon all of the XNOR gates of a particular one said array of said XNOR gates having yielded a “

1”

bit, said AND gate to which said particular one array of said XNOR gates is connected will yield a “

1”

bit;

An array of enable latches equal in number to the number of said AND gates, to the gates of said enable latches are respectively connected the outputs of said AND gates; and

An array of voltage sources equal in number to the number of said enable latches and being connected respectively to each of said enable latches, whereby

The receipt of a “

1”

bit by a particular one of said enable latches from the said AND gate connected thereto will cause a voltage from that particular said voltage source that is connected to said particular one of said enable latches to pass through said particular one of said enable latches, with said voltage then serving as a “

1”

bit to enable that pass transistor within PS 100 to which enable latch is connected, as one part of structuring a circuit using the LNs 102 of PS 100.

10. The electronic circuit of claim 8 wherein said signal code selector comprises:

A first DMUX having lines therefrom connecting to three second DMUXs, pertaining respectively to the drain, gate, and source terminals of an operating transistor serving as an originating transistor, with a pass transistor to be enabled being connected to that one of said drain, gate, and source terminals of said originating transistor that had been selected by said first DMUX;

An array of second DMUXs, each of which

connects to one of said lines connecting from said first DMUX, and

has two lines connected thereto that pertain to the upward and rightward directions from said originating transistor, and

with said pass transistor that is to be enable being directed in that direction as had been selected by said second DMUX; and

An array of six third DMUXs, each of which connects to one of said two lines connecting

from one of said three second DMUXs, and

has three lines connected therefrom that pertain respectively to the drain, gate, and source terminals of an operating transistor acting as a receiving transistor; and

An array of six 3-line code enablers, with each of said 18 code enablers being connected to one of said three lines connecting from one of said six third DMUXs and having an enabling lines connecting therefrom;

with

Each of said lines being connected to the gate terminal of a pass transistor; and

One or more voltage sources that collectively will connect to each of said code enablers, whereby a “

1”

bit received by one of said code selectors through said first, second, and third DMUXs will direct voltage from said voltage sources to the gate terminal of that pass transistor that is connected to that terminal of said receiving transistor as had been selected by said first, second, and third DMUXs.

11. The electronic circuit of claim 7 further wherein said processing space has a manifold-like construction, comprising:

A multiplicity of manifold lines having first ends that connect indirectly to at least operational transistor that is physically located on an outer surface of said processing space, along an edge of said processing space, or at a corner of said processing space, and second ends that connect directly to respective LNs 102 that are physically located at opposite positions with respect to the location of each said at least one LN 102, within an opposite surface, an opposite edge, or an opposite corner, respectively;

A multiplicity of manifold line pass transistors of a number that is equal to the number of said manifold lines, connected respectively to said first ends of said manifold lines that connect indirectly to said at least one operational transistor, and further connected to at least one terminal of said at least one operational transistor, thereby making direct connection thereto; and

A multiplicity of manifold line pass transistor enablers of a number that is equal to the number of said manifold line pass transistors and are connected respectively to each of said manifold line pass transistors, whereby

an enabling voltage from one of said manifold line pass transistor enablers to that manifold line pass transistor to which connected will cause said manifold line pass transistor to become conductive, thereby

enabling a signal voltage to be conveyed from a terminal of a first operational transistor to a terminal of a second operational transistor that is physically located oppositely to said first operational transistor, said first and second operational transistors being located on opposite sides, opposite edges, or opposite corners of said processing space. cm 12. A circuit code selector comprising;

A number of circuit code input nodes each being connected respectively to a first input to an XNOR gate;

said XNOR gates being equal in number to the number of said circuit code input nodes;

Reference latches holding the respective values “

0” and

“

1”

that connect respectively to a second input to each of said XNOR gates, whereupon the entry of the same bit value from said circuit code input node to said first input to said XNOR gate as the bit value of said code reference latch that is connected to the second input to said XNOR gate will bring about a “

1”

bit output from said XNOR gate;

wherein

The said “

0” and

“

1”

bit values that are held in said reference latches are established in such a manner as to form a number of bit combinations of a pre-selected bit length, each of said bit combination being distinct in terms of the bit values held from every other bit combination formed in that same manner;

Each of said distinct bit combination is connected to said second inputs of a particular one of a number of arrays of XNOR gates wherein the bit length of each said array of XNOR gates is the same as the bit lengths of said distinct bit combinations,

Each XNOR gate of a particular said array of XNOR gates to which any one of said bit combinations is sent from said reference latches is a different XNOR gate from any XNOR gate to which a different one of said bit combinations has been sent;

A number of AND gates each having a number of inputs equal to the number of XNOR gates contained in each of said arrays of said XNOR gates, the output of each of said XNOR gates of a particular array of said XNOR gates being connected respectively to each of said inputs to that one of said AND gates to which are connected the outputs of those said XNOR gates that are connected to the particular AND gate, whereby

Upon all of the XNOR gates of a particular one said array of said XNOR gates having yielded a “

1”

bit, said AND gate to which said particular one array of said XNOR gates is connected will yield a “

1”

bit;

An array of enable latches equal in number to the number of said AND gates, to the gates of said enable latches are respectively connected the outputs of said AND gates; and

An array of voltage sources equal in number to the number of said enable latches and being connected respectively to each of said enable latches, whereby

The receipt of a “

1”

bit by a particular one of said enable latches from the said AND gate connected thereto will cause a voltage from that particular said voltage source that is connected to said particular one of said enable latches to pass through said particular one of said enable latches, with said voltage then serving as an enable bit to enable a pass transistor for some useful purpose.

13. A signal code selector comprising:

A first DMUX having a predetermined first lines number of first code lines connected thereto, wherein a selection code of a predetermined bit length is to be entered into said first DMUX;

At least an array of second DMUXs each having a second lines number of second code lines connected thereto, said second DMUXs being of a number corresponding to said first lines number of first code lines, each said second DMUX further being connected to respective ones of said first code lines and having an array code that will determine which of said DMUXs is to connect to which of said first code lines;

(n−

2) additional arrays of DMUXs, each said DMUX having an (n−

2)^th lines number of (n−

2)^th code lines connected thereto, thereby to establish a sequence of m arrays of DMUXs, and

A set of code enablers having an enabler code of sufficient length to identify each of said code enablers individually;

wherein

Said pre-determined bit length of said selection code is determined by a summation of the bit lengths of a series of n code segments, each said code segment being one of said array codes and having such bit length as may be necessary to express in binary code the lines number pertaining to each particular one of said arrays of DMUXs, and wherein further

Said selection code is formed by concatenating together both all of said array codes and said enabler code, whereby the code received by each successive array of DMUXs will be the code as received by the array of DMUXs that was just previous thereto, but from which the particular array code that had pertained to said array of DMUXs that was just previous thereto will have been removed, until only code segment left is said enabler code, that will select the final destination as is expressed by said selection code as a whole.

14. An electronic circuit for information processing having a processing space comprising:

A multiplicity of pairs of input nodes for accepting binary bits that constituting a binary code;

A multiplicity of pairs of NAND gates equal in number to the number of said pairs of said input nodes, wherein

a first said NAND gate of one of said pairs of said NAND gates has a first input of one of said pairs of said input nodes connected to a first input of said first one of said NAND gates of said pair of said NAND gates; and

a second said NAND gate of said pair of said NAND gates has a second input of said one of said pairs of said input nodes connected to a second input of said second one of said NAND gates of said pair of said NAND gates;

At least one instance of a pair of reference latches, wherein

a first one of said reference latches of said at least one instance of a pair of reference latches has a “

0”

bit stored therein and is connected to said second input of said first one of said NAND gates of a pair of said NAND gates; and

the second one of said reference latches of said at least one instance of a pair of reference latches has a “

1”

bit stored therein and is connected to said second input of said second one of said NAND gates of a pair of said NAND gates;

A multiplicity of 2-bit AND gates equal in number to the number of said pairs of NAND gates, from which each one of said two inputs thereto is connects to the output of a respective one of said NAND gates of said one of said pairs of NAND gates;

A multiplicity of enable latches equal in number to and connected respectively to each of said multiplicity of 2-bit NAND gates; and

A multiplicity of voltage sources equal in number to and connected respectively to each of said multiplicity of said enable latches, whereby

The receipt by one or more of said enable latches of a “

1”

bit from one or more of said AND gates to which each one of said one multiplicity of enable latches is connected will cause a voltage from said respective one or more voltage sources connected to respective one or more enable latches to pass therethrough to enable one or more pass transistors that are connected to one or more respective ones of said multiplicity of said enable latches, and wherein further,

Said interconnected combination of said pairs of said input nodes, pairs of NAND gates, pairs of reference latches, an AND gate, an enable latch and a voltage source operates as a single, independent unit with respect to the use of a 2-bit code to enable a pass transistor or for like purpose, and can be so employed, singly or in groups of said units, said groups being of arbitrary size, working cooperatively, without regard to what may be the physical locations of individual ones of said groups of said units.

15. A nested multi-level data selector and counter comprising:

A first data selector circuit including a first data counter, wherein said first data selector circuit selects out from a first set of datum segments constituting a defining code for a first item in a body of data a first portion in accordance with first pre-defined category codes and divides said first portion into a number of first pre-defined groups, while accumulating a count of the datum segments that are placed into each of said number of pre-defined groups, then continuing that process until the entirety of said items in said body of data have been so treated;

At least a second data selector circuit, respectively including at least a second counter, wherein with respect to successive ones of said items in said body of data, each of said at least a second data selector circuits selects at least a second portion of said array of datum segments, said at least a second portion of said array of datum segments constituting a first remainder of said body of data following the selecting out from said body of data of said first portion of said array of datum segments constituting said body of data by said first data selector circuit, at least a second number of at least second pre-defined groups in accordance with at least second pre-defined category codes, while accumulating a count of the datum segments that are placed into said at least a second number of at least second pre-defined groups, with that selecting out from said first remainder said second portion of said array of datum segments then leaving a second remainder of said body of data; and

At least a first data distribution circuit that as to each of said items in said body of data, routes each of said at least second pre-defined groups into that one of said first pre-defined groups that pertains to each of said items, whereby each item will have been placed within a combination group defined in accordance with both said first pre-defined category code and said at least second pre-defined category codes and having a combination count derived from both said first data counter and said at least second data counter, then continuing that process until all of said items in said body of data have been so treated;

whereby

Said first data selector circuit, said first counter, each of said at least second data selector circuits, each of said at least second counter, and each of said at least a first data distribution repeat said process with respect to each first remainder and each of said at least second remainder until no portions of said group defining code remain and all of said items in said body of data have been counted and placed into cumulative combination groups defined by all of the successive pre-defined category codes.

16. Apparatus for making electrically conductive connections to transistor terminals on a planar integrated circuit, comprising:

An upper interconnect plane further comprising a multiplicity of elongate contact pins disposed in a defined first pattern thereon and extending downward from said plane, and

a corresponding multiplicity of incoming signal lines, with each of said signal lines being connected to the proximal end of one of said contact pins; and

A lower interconnect plane further comprising a multiplicity of elongate contact orifices disposed in a defined second pattern thereon and sized to receive said contact pins in a snug fit therewithin so as to establish a positive electrical contact, said second pattern corresponding to said first pattern, whereby each of said contact pins will be inserted into and establish electrical contact with a corresponding one of said contact orifices upon bringing together said upper interconnect plane and said lower interconnect plane;

a corresponding multiplicity of connections from the distal ends of each of said contact orifices to a terminal of a transistor; and

means for maintaining a positive pressure of said upper interconnect plane against said lower interconnect plane.

17. The apparatus of claim 16 wherein said connection from a distal end of one of said contact orifices is to a terminal of a transistor that is disposed in the plane of an upper integrated circuit layer that is in juxtaposition with said lower interconnect plane.

18. The apparatus of claim 16 wherein said connection from a distal end of one of said contact orifices is through a wire that extends through a via within said upper integrated circuit layer to a terminal of a transistor that is disposed in the plane of a lower integrated circuit layer that lies below said upper integrated circuit layer.

19. The apparatus of claim 16 wherein said connections from said distal ends of said contact orifices connect to terminals of an array of operational transistors within a processing space, and said incoming signal lines connect from pass transistors within a processing space of a separate integrated circuit, disposed on the outwardly facing surfaces of a like construct of said upper and lower interconnect planes, thereby to connect said pass transistors within said processing space of one integrated circuit to terminals on said operational transistors within a processing space of a second integrated circuit.

20. The apparatus of claim 16 wherein said incoming signal lines extend from terminals of operational transistors that lie geometrically opposite to said terminals that receive said signal lines, thereby to provide wrap-around connections between said terminals.

21. A direct contact connector to an integrated circuit having exposed electrical contact terminals, comprising:

a wrap cap for removable attachment to a plane surface of an integrated circuit wherein said plane surface includes a multiplicity of electrical contact points laid out in a predetermined pattern therein, said wrap cap further comprising;

a lower manifold contact plane including a multiplicity of contact orifices, each said contact orifice being connected to the gate terminal of a pass transistor that connects between a connecting line and one of a multiplicity of contact studs laid out within said lower manifold contact plane in a pattern that corresponds to said predetermined pattern;

an upper manifold contact plane including a multiplicity of contact pins, each said contact pin being aligned with and being sized to fit within one of said contact orifices, whereby a downward movement of said upper manifold contact plane relative to said lower contact plane will place each of said contact pins within a corresponding one of said contact orifices so as to make electrical contact thereto;

a wrap cap cover disposed over said upper manifold contact plane having attachment means to said lower manifold contact plane, wherein such attachment will hold said contact pins in a pressure fit within said contact orifices;

a manifold line control cable comprising a multiplicity of wires extending respectively to each of said contact pins from an external array of voltage sources and being elastically attachable to the ensemble of said wrap cap cover, said upper manifold contact plane, said lower contact plane, and said integrated circuit, whereby pressure contact is made respectively between separate ones of said contact studs and corresponding ones of said electrical contact points, whereby voltages become applied to those ones of those electrical contact points for which said corresponding contact pins have applied a voltage to the corresponding ones of said gate terminals of said pass transistors.

22. The direct contact connector of claim 21 wherein said electrical contact points within said integrated circuit lie at least at positions corresponding to a V_dd connection, a GND connection, the gate terminal of a pass transistor that connects between the drain terminal of each said operational transistor and said V_dd connection, the gate terminal of a pass transistor that connects between the source terminal of each said operational transistor and GND, and the gate terminals of an array of pass transistors that connect respectively between the respective drain, gate, and source terminals of one operational transistor to each of the drain, gate, and source terminals of at least one adjacent operational transistor.

23. A two-level integrated circuit comprising a two-dimensional array of operational transistors wherein:

In a first, lower level,

a first array of three interconnection lines that each connect at opposite ends thereof through a pass transistor to the drain, gate and source terminals of a next adjacent operational transistor;

Also in said first, lower level,

a second array of three interconnection lines that each connect at opposite ends thereof through a pass transistor to the drain, gate and source terminals of a next adjacent operational transistor,

wherein said second array is disposed at right angles to said first array, from which disposition a crossing point is defined between each line of said first array and a corresponding line of said second array, with connection being made between each said line of said first array and each said line of said second array at each of said crossing points;

In a second, upper level, one of said operational transistors wherein

said drain and source terminals are disposed respectively at opposite ends of an interconnecting line, each said terminal then connecting first to a post through a first pass transistor and then to a second pass transistor; and

a gate terminal disposed a right angle to said interconnecting line between said drain and source terminals;

wherein said second pass transistor extends on to V_dd in the case of said drain terminal, to an external input as to said gate terminal, and to GND as to said source terminal; and

Said operational transistor and associated pass transistors are disposed at an angle relative to the arrays of pass transistors in said lower level such that the point in said second, upper layer, along the connection from respective drain, gate and source terminals to said pass transistors connected thereto, is positioned to lie over and is connected to the connection point in said first, lower level at which said interconnection lines lying at right angles one with the other are connected.

24. A passive binary circuit comprising:

an array of operational transistors having drain, gate, and source terminals, wherein said drain terminal connects to V_dd through a pass transistor, said gate terminal connects to an external signal source through a pass transistor, and said source terminal connects to GND through a pass transistor; and

each of said drain, gate, and source terminals connects in at least one direction to each of the drain, gate, and source terminals of a second operational transistor;

whereby an active binary circuit can be formed by providing enabling voltages to one or more of said pass transistors.

25. A method of determining IN_j values for the operational transistors required for the structuring of a circuit, comprising the following steps, not necessarily to be executed in the order shown:

a. Defining a drawing space having the required dimensions and adequate size to accommodate the drawing therein of one or more circuits of such types as may be desired, said drawing space having representations of a multiplicity of operational transistors evenly distributed therein in a regular rectangular array of said dimensions and size;

b. Within said drawing space, providing sequential Location Indicators (LI_i) for said operational transistor representations using ordinary cardinal numbers through the range 1≦

i ≦

M, where M is the number of operational transistor representations within said drawing space, such that the “

1”

operational transistor representation is located at an end of a one-dimensional drawing space, at a corner of a two dimensional drawing space, and at a vertex of a three dimensional drawing space, with the values thereof in cardinal numbers then to increase in a pre-selected direction in units of one as to the “

x”

axis, in a pre-selected direction in units of the maximum x axis length along the “

y”

axis, if any, and in a pre-selected direction in units of the product of the maximum x axis length and the maximum y axis length along the “

z”

axis, if any;

c. Providing a processing space having the required dimensions and adequate size to accommodate the structuring therein of one or more circuits of such types as may be desired, said processing space having a multiplicity of operational transistors evenly distributed therein in a regular rectangular array of said dimensions and size;

d. Within said processing space, providing sequential Index Numbers (IN_j) for said operational transistors using ordinary cardinal numbers through the range 1≦

j≦

N, where N=M is the total number of operational transistors within said processing space, such that the “

1”

operational transistor is located at an end of a one-dimensional processing space, at a corner of a two dimensional processing space, and at a vertex of a three dimensional processing space, with the values thereof in cardinal numbers then to increase in a pre-selected direction in units of one as to the “

x”

axis, in a pre-selected direction in units of the maximum x axis length along the “

y”

axis, if any, and in a pre-selected direction in units of the product of the maximum x axis length and the maximum y axis length along the “

z”

axis, if any, and then taking the respective binary expressions of said cardinal numbers to obtain the actual IN₁ values;

e. Identifying an operational transistor within a circuit sought to be structured at which an input to said circuit would be entered;

f. Identifying one of said operational transistors within said processing space at which data will be entered;

g. Within said drawing space, providing a drawing of a circuit sought to be structured as to which that said operational transistor that was identified in step e) is correlated as to location with that said operational transistor that was identified in step f and that in a regular rectangular array shows

(i) all of one or more operational transistors that are to be used in said circuit, any additional operational transistors that would be needed to bring those operational transistors between which connection is to be made into a mutually orthogonal relationship,

(ii) any additional operational transistors that lie between two operational transistors that are to be connected together, wherein the relative locations of said operational transistors form a pattern that conforms to the locations of respective ones of said operational transistors within said processing space, and

(iii) orthogonal connections between those of said operational transistors as to which said connections are parts of said circuit;

h. In the event any of said connections that are provided in step g(ii) are seen to pass through one or more intervening operational transistors in order to reach an operational transistor to which connection is to be made, mark each of said intervening operational transistors as being a BYPASS gate; and

i. Correlating the LI_i locations of the remaining ones of said operational transistor representations in said drawing space with the IN_j locations of said operational transistors in said processing space.

26. The method of claim 25 wherein step (i) is accomplished by carrying out the following steps:

(i)(1) Providing a transparent overlay of the size and shape of said drawing space having regions marked therein that replicate the pattern of the operational transistor representations in said drawing space, one of which said regions is identified as being a reference region having the Location Indicator LI₁;

(i)(2) Determining the maximum length of said processing space in the x direction, defining such length as x_M;

(i)(3) Determining the maximum length of said processing space in the y direction, if any, defining such length as y_M;

(i)(4) Providing at the locations of each of the remaining regions on said overlay a formula consisting of an appropriately reduced form of the equation

LI_i=LI₁±

r₁

as to a one dimensional array,

LI_i=LI₁±

r_i±

k_ix_M

as to a two-dimensional array, and

LI_i=LI₁±

r₁±

k_ix_M±

I₁(x_M^*y_M)

as to a three-dimensional array, where LI₁ is the location of said reference operational transistor, r_i is the distance of the i^th operational transistor from the LI₁ location to the right or left along the x axis of the array, k is the distance of the i^th operational transistor from the LI₁ location up or down along the y axis of the array, and I₁ is the distance of the i^th operational transistor from the LI₁ location inward or outward along the z axis of the array;

(i)(5) Selecting a location IN₁ within said processing space at which the structuring of said circuit is to be initiated;

(i)(6) Placing said overlay over said processing space such that the LI₁ location in said overlay lies over said IN₁ operational transistor;

(i)(7) Successively applying the appropriate equations of step (i)(4) to each of the operational transistors of said circuit so as to obtain the successive IN_j values.

27. The method of claim 25 wherein step (i) is accomplished by carrying out the following steps:

(i)(1) Providing a transparent overlay of the size and shape of said drawing space having regions marked therein that replicate the pattern of the operational transistor representations in said drawing space, one of which said regions is identified as being a reference region having the Location Indicator LI₁;

(2) Selecting a location IN₁ within said processing space at which the structuring of said circuit is to be initiated;

(3) Placing said overlay over said processing space such that the LI₁ location in said overlay lies over said IN₁ operational transistor;

(4) From the locations of said operational transistor representations in said overlay that had been marked as to be used, identifying the corresponding locations of said operational transistors in said processing space;

(5) Determining the maximum length of said processing space in the x direction, defining such length as x_M;

(6) Determining the maximum length of said processing space in the y direction, if any, defining such length as y_M;

(7) Determining the x, y, and z coordinates of each of said operational transistors as had been identified in step (4); and

(8) Using the x, y, and z coordinates as had been determined in step (5), calculating the LI_i value of each of said operational transistors as had been identified in said processing space in step (i)(4) using the equation

LI_i(x,y,z)=X_M(Y_M(z−

1)+y−

1)+x;

and

(9) Converting the LI_i values derived from step (i)(8) into binary IN_j values.

28. A method of laying out a set of masks for the fabrication of an integrated circuit comprising an array of a multiplicity of operational transistors, each said operational transistor having a source, a gate, a drain, and an input terminal, wherein each of said source, gate, and drain terminals of a first said operational transistor connects through a pass transistor to each of said source, gate, and drain terminals of at least one other operational transistor in at least one of four orthogonal directions extending from said first operational transistor, such that said inter-operational transistor connections lie orthogonally to one another, comprising the following steps, not necessarily being executed in the order shown:

(1) In an operational mask level, forming patterns for an operational transistor having

(a) a source terminal extending outwardly therefrom in a first direction along a source line that is central to said source terminal and includes a source pass transistor along said source line;

(b) a drain terminal extending outwardly therefrom in a second direction along a drain line that is central to said drain terminal, opposite to said first direction, collinear with said source line, and includes a drain pass transistor along said drain line;

(c) a gate terminal that is disposed centrally between said source and drain terminals and a connection thereto that extends outwardly therefrom along a gate line that is orthogonal to said source and drain lines;

(2) In an interconnection mask level, forming patterns for a number of conductor channels along lines that

(a) in a first set thereof lie mutually parallel at predetermined distances therebetween in a nghtwardly and leftwardly direction;

(b) in a second set thereof, if any, lie mutually parallel at predetermined distances therebetween in an upwardly and downwardly direction, such that each one of said first set of conductor channels defines a crossover point with a corresponding one, if any, of corresponding ones of said second set of conductor channels;

(3) rotating said operational mask pattern relatively to said interconnection mask pattern about an axis that lies centrally to said gate terminal and orthogonally to both said source and drain line and said gate line, through such angle as is necessary

(a) to bring respective points along each of said source, gate and drain lines of said operational mask pattern into superposition with corresponding points along respective ones of said conductor channels of said interconnection mask pattern, respectively, if said interconnection mask pattern were placed into juxtaposition with said operational mask pattern,

(b) wherein said predetermined distances between said parallel lines within at least a first set of conductor channels have been established in such manner that

(i) a single location along each of said source, gate, and drain lines in said operational mask pattern lies in superposition with a single location along each of respective ones of said source, gate, and drain conductor channels in one of said leftward and rightward or upward and downward sets of said interconnection mask pattern; and

(ii) wherein if both a leftward and rightward and an upward and downward set of conductor channels are present, each of said points of superposition between points along each of said source, gate, and drain lines in said operational mask pattern with corresponding ones of one set of said source, gate, and drain conductor lines in said interconnection mask pattern is also a point of superposition as to that other of said source, gate, and drain conductor lines in said interconnection mask pattern;

(4) forming an electrical connection between each of the superposition points along said source, gate, and drain lines of said operational mask pattern and

(a) those points along said source, gate and drain channels of at least said first set of source, gate, and drain conductor channels in said interconnection mask pattern; and

(b) those points along said source, gate and drain channels of said second set of source, gate, and drain conductor channels, if present, in said interconnection mask pattern; and

(c) with those points along said source, gate and drain channels of said second set of source, gate, and drain conductor channels, if present, in said mask pattern; and

(5) providing at distal ends of each of the source, gate, and drain conductor lines within the interconnection mask pattern further patterning that will divide each single source, gate, and drain conductor line into separate source, gate, and drain lines that will be alignment with and connectible to corresponding conductor lines in an adjacent operational transistor; and

(6) replicating the superimposed interconnection and operational mask patterns of step (5) in one or more orthogonal directions that lie collinearly with said conductor lines within said interconnection pattern, said replicating to be carried out that number of times as is necessary to construct an array of said operational transistors of such dimensions and size as were desired for said integrated circuit.