Load/store unit for a processor, and applications thereof

• US 20080082794A1
• Filed: 09/29/2006
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Nangia, Era K., Ni, Michael, Yu, Meng-Bing
• Granted Patent: US 9,946,547 B2
• Time in Patent Office: Days
• US Class Current: 712/218
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Claims

1. A processor that executes instructions out-of-program-order, comprising:

a load/store queue that includes a plurality of entries configured to store information associated with a particular class of instructions;

a load/store graduation buffer that includes a plurality of entries configured to store pointers to the load/store queue; and

control logic coupled to the load/store queue and the load/store graduation buffer,

wherein, upon graduation of a first instruction, belonging to the particular class of instructions, that is associated with a cache miss, the control logic causes a first pointer to be stored in the load/store graduation buffer that points to an entry in the load/store queue associated with the first instruction.

2. The processor of claim 1, wherein the particular class of instructions includes instructions that read data from memory and that write data to memory.

3. The processor of claim 1, wherein the particular class of instructions includes instructions that read data from a register of a coprocessor.

4. The processor of claim 1, wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

5. The processor of claim 1, wherein each entry of the load/store queue includes a field for storing exception information.

6. The processor of claim 1, wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

7. The processor of claim 1, wherein each entry of the load/store graduation buffer includes a field for storing exception information.

8. A system, comprising:

a processor that includes

a load/store queue that includes a plurality of entries configured to store information associated with a particular class of instructions,

a load/store graduation buffer that includes a plurality of entries configured to store pointers to the load/store queue, and

control logic coupled to the load/store queue and the load/store graduation buffer,

wherein, upon graduation of a first instruction, belonging to the particular class of instructions, that is associated with a cache miss, the control logic causes a first pointer to be stored in the load/store graduation buffer that points to an entry in the load/store queue associated with the first instruction; and

a memory coupled to the processor.

9. The system of claim 8, wherein the particular class of instructions includes instructions that read data from memory and that write data to memory.

10. The system of claim 8, wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

11. The system of claim 8, wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

12. A tangible computer readable storage medium that includes a processor embodied in software, the processor comprising:

a load/store queue that includes a plurality of entries configured to store information associated with a particular class of instructions;

a load/store graduation buffer that includes a plurality of entries configured to store pointers to the load/store queue; and

control logic coupled to the load/store queue and the load/store graduation buffer,

wherein, upon graduation of a first instruction, belonging to the particular class of instructions, that is associated with a cache miss, the control logic causes a first pointer to be stored in the load/store graduation buffer that points to an entry in the load/store queue associated with the first instruction.

13. The tangible computer readable storage medium of claim 12, wherein the particular class of instructions includes instructions that read data from memory and that write data to memory.

14. The tangible computer readable storage medium of claim 12, wherein each entry of the load/store queue includes a virtual address field for storing virtual address bits, a physical address field for storing physical address bits, and a data field for storing data bits.

15. The tangible computer readable storage medium of claim 12, wherein the pointers stored in the load/store graduation buffer are completion buffer identification values.

16. The tangible computer readable storage medium of claim 12, wherein the processor is embodied in hardware description language software.

17. The tangible computer readable storage medium of claim 12, wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.

18. A method for maintaining uncached load/store order in a processor that executes instructions out-of-program-order, comprising:

storing information associated with memory access instructions in a load/store queue, the load/store queue having a plurality of entries, each entry configured for storing information associated with a single instruction;

upon graduation of a memory access instruction associated with a cache miss, storing a pointer value in a first-in-first-out load/store graduation buffer that points to an entry in the load/store queue associated with the instruction; and

processing instructions associated with pointers stored in the load/store graduation buffer according to an order of the pointers stored in the load/store graduation buffer.

19. The method of claim 18, further comprising:

stalling processing of instructions associated with pointers stored in the load/store graduation buffer until a read request associated with a particular instruction is sent to a bus interface unit of the processor.

20. The method of claim 18, further comprising:

stalling processing of instructions associated with pointers stored in the load/store graduation buffer until a write request associated with a particular instruction is accepted by a write-back buffer of the processor.

21. The method of claim 18, wherein the processing step comprises:

allocating an entry for an instruction in a fill/store buffer.

22. The method of claim 18, wherein the processing step comprises:

allocating an entry for an instruction in a load data queue.

23. A method for processing memory access instructions in a processor that executes instructions out-of-program-order, comprising:

storing a completion buffer identification value for a graduating memory access instruction in a load/store graduation buffer;

using bits of the stored completion buffer identification value to access an entry of a load/store queue associated with the instruction;

retrieving information from the load/store queue entry; and

determining whether to allocate an entry for the instruction in a fill/store buffer based on the retrieved information.

24. The method of claim 23, wherein the retrieving step comprises:

retrieving information about whether data to be loaded in to a register of the processor is available in a data cache.

25. The method of claim 23, further comprising:

determining whether to allocate an entry for the instruction in a load data queue based on the retrieved information.