Flexible Microprocessor Register File

• US 20080082798A1
• Filed: 09/29/2006
• Published: 04/03/2008
• Est. Priority Date: 09/29/2006
• Status: Abandoned Application

• Current Assignee: RPX Corporation
• Original Assignee: 3DLabs Incorporated Limited (Creative Technology Ltd.)
• Inventors: Bloomfield, Jonathan, Robson, John, Murphy, Nick
• Application Number:
  US11/537,425
• Publication Number:
  US 20080082798A1
• Time in Patent Office: Days
• US Class Current: 712/223
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports

Abstract

Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Claims

1. A method of selectably transposing data accessed in a register, comprising the actions of:

storing data in n memory segments, each having n data lanes at the output thereof; and

selectably connecting each of n data but segments to a respective one of said n2 data lanes;

whereby a desired data transposition is provided at the time of register access without register-to-register transfers.

2. The method of claim 1, wherein each said data lane carries 8 bits of data.

3. The method of claim 1, wherein said selectably connecting step is performed by activating only n of a total of n2 multiplexers.

4. The method of claim 1, wherein n=4.

5. A method of viewing data within a register file, comprising the steps of:

enabling a transpose function with respect to a selected register; and

modifying a view of the selected register, as seen by an external access, such that data in the selected register is replaced with data from a plurality of consecutive registers.

6. The method of claim 5, wherein said modifying step effectively rotates the apparent orientation of data in said selected register.

7. The method of claim 5, wherein said modifying step effectively applies bytewise transposition to said view.

8. The method of claim 5, wherein said modifying step effectively applies wordwise transposition to said view.

9. A method of viewing data within a register file, comprising the steps of:

identifying a first source byte in a register;

copying data from the first source byte into a first destination byte of the register;

identifying a second source byte in the register; and

copying data from the second source byte into a second destination byte of the register.

10. (canceled)