Edge connect wafer level stacking

• US 20080083976A1
• Filed: 02/09/2007
• Published: 04/10/2008
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Oganesian, Vage, Haba, Belgacem
• Granted Patent: US 8,513,789 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Claims

1. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements;

forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements; and

forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

2. The method of claim 1, wherein the first subassembly and the second subassembly include saw lanes, wherein during the step of forming the microelectronic assembly the saw lanes of the first subassembly are aligned with the saw lanes of the second subassembly and the notches are formed at the saw lanes of the respective assemblies.

3. The method of claim 1, wherein the notches only extend partially through the first subassembly.

4. The method of claim 3, further comprising the step of entirely dicing through the saw lanes of the first assembly to form individual stacked packages.

5. The method of claim 1, wherein at least some of the plurality of microelectronic elements of the first and second subassemblies include contacts exposed at their respective front faces, wherein at least some of the traces are electrically connected at least some of the contacts.

6. The method of claim 1, wherein during the step of forming a microelectronic assembly a first face of the first subassembly is adhered to a second face of the second subassembly by an adhesive.

7. The method of claim 1, wherein some of the traces of the first subassembly are offset from some of the traces of the second assembly and a lead formed on the side wall of a notch is in contact with a trace of one of the subassemblies but not with a trace of the other.

8. A method of manufacturing a stacked package comprising the steps of:

aligning saw lanes of a first wafer with saw lanes of a second wafer such that the saw lanes of one wafer are positioned above the saw lanes of the other wafer, each of the first and second wafers having a plurality of traces that extend toward the saw lanes;

exposing the plurality of traces by at least partially cutting through the saw lanes of the first wafer and second wafer; and

electrically connecting leads with at least some of the exposed plurality of traces.

9. The method of claim 8, wherein the first and second wafers include a plurality of microelectronic elements in electrical contact with the plurality of traces.

10. The method of claim 9, further comprising attaching the first wafer to the second wafer after the saw lanes of the two wafers are aligned.

11. The method of claim 9, wherein the leads include first ends that extend to a front face of one of the wafers.

12. The method of claim 11, wherein the first ends of the leads include solder bumps for attaching to an additional microelectronic device.

13. The method of claim 8, further comprising aligning the saw lanes of at least one additional wafer with the saw lanes of the first and second wafers, wherein during the step of exposing the plurality of traces of the first and second wafer a plurality of traces of the at least one additional wafer is also exposed.

14. A stacked microelectronic package comprising:

a first subassembly and a second subassembly coupled to each other, each first and second subassembly including at least one edge and a plurality of traces exposed at the respective at least one edge;

a plurality of leads attached to at least some of the plurality of traces of the first subassembly and second subassembly, wherein the plurality of leads extend about the at least one edge of both the first subassembly and second subassembly.

15. The stacked microelectronic package of claim 14, wherein the first subassembly and second subassembly each include at least one microelectronic chip.

16. The stacked microelectronic package of claim 15, wherein each of the microelectronic chips of the first subassembly and second subassembly include a front face, an oppositely-facing rear face and a plurality of contacts exposed at each of the front faces of the microelectronic chips, wherein the plurality of traces of the first subassembly and second subassembly extend outwards from the plurality of contacts exposed at the front faces of the microelectronic chips.

17. The stacked microelectronic package of claim 16, wherein the first subassembly and second subassembly each include at least one additional edge, wherein at least some of the plurality of traces of each of the first and second subassemblies extend to the at least one additional edge of the first and second assemblies.

18. The stacked microelectronic package of claim 17, wherein at least some of the plurality of leads extend about the at least one additional edge of the first and second subassemblies.

19. The stacked microelectronic package of claim 18, wherein the second subassembly includes a front surface, wherein the plurality of leads have first ends that are exposed at the front surface of the second subassembly

20. The stacked microelectronic package of claim 19, further comprising at least one additional subassembly attached to said first and second subassembly, wherein the at least one additional subassembly is in electrical communication with at least some of said plurality of leads

21. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a substrate, stacking a second subassembly including a plurality of microelectronic elements above said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements;

forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements; and

forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

22. The method of claim 21, wherein the substrate, the first subassembly and the second subassembly include saw lanes, wherein during the step of forming the microelectronic assembly the saw lanes of the first subassembly are aligned with the saw lanes of the substrate, the saw lanes of the second subassembly are aligned with the saw lanes of the first subassembly and the notches are formed at the saw lanes of the respective subassemblies.

23. The method of claim 22, wherein a relief channel, aligned with the saw lanes of the substrate, is formed partially through the substrate.

24. The method of claim 21, wherein the leads include first ends that extend to an upper face of the second subassembly.

25. The method of claim 24, wherein the leads include second ends that extend to an upper face of the substrates.

26. The method of claim 23, wherein the step of forming notches does not include forming notches in the substrate.

27. The method of claim 22, further comprising the step of dicing through the saw lanes of the substrate to form individual stacked packages.

28. The method of claim 21 wherein during the step of forming a microelectronic assembly a first face of the first subassembly is adhered to a second face of the substrate by an adhesive.

29. The method of claim 21, wherein at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend across said saw lanes of said first subassembly and said second subassembly.

30. The method of claim 21, wherein the step of forming notches includes forming initial notches in at least said first subassembly so as to expose said traces and filling said initial notches with adhesive so as to cover said traces and forming initial notches in at least said second subassembly so as to expose said traces and filling said initial notches with adhesive so as to cover said traces and forming said notches in said adhesive so as to expose the traces of at least some of the plurality of microelectronic elements.

32. The method of claim 30 wherein said initial notches are formed by etching.

31. A method of making a microelectronic subassembly, the method comprising the steps of:

forming initial notches in a first subassembly, including a plurality of microelectronic elements, said subassembly having traces that extend to respective edges of the microelectronic elements, so as to expose said traces;

filling said initial notches with adhesive so as to cover said traces; and

forming notches in said adhesive so as to expose the traces of at least some of the plurality of microelectronic elements.

33. The method of claim 31 wherein said traces remain substantially intact after etching said notches.

34. A stacked microelectronic package comprising:

four subassemblies and a substrate stacked to each other, each subassembly including at least one microelectronic chip;

the package having a stack thickness of no more than 155 micrometers.

35. A stacked microelectronic package comprising:

four subassemblies stacked to each other, each subassembly including at least one microelectronic chip;

the package having a stack thickness of no more than 125 micrometers.

36. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and

then

forming initial notches in said first subassembly so as to expose said traces and coating an adhesive layer on said first subassembly so as to fill said initial notches with adhesive and cover said traces; and

then

stacking a second subassembly including a plurality of microelectronic elements onto said adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and

then

forming initial notches in said second subassembly so as to expose said traces and coating an adhesive layer on said second subassembly so as to fill said initial notches with adhesive and cover said traces; and

then

forming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements;

and forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

37. The method of claim 36, wherein the substrate, the first subassembly and the second subassembly include saw lanes, wherein after stacking the microelectronic assembly, the saw lanes of the substrate, the first subassembly and the second subassembly are aligned and, after coating the adhesive layer on the second subassembly, the notches are formed at the saw lanes of the respective subassemblies.

38. The method of claim 37, wherein a relief channel, aligned with the saw lanes of the substrate, is formed partially through the substrate prior to stacking said first subassembly onto the adhesive layer of a substrate.

39. The method of claim 37, further comprising the step of dicing through the saw lanes of the substrate to form individual stacked packages.

40. The method of claim 36, wherein the step of forming notches does not include forming notches in the substrate.

41. The method of claim 38, wherein the step of forming notches does not include forming notches in the substrate.

42. The method of claim 36, wherein at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend across said saw lanes of said first subassembly and said second subassembly.