Edge connect wafer level stacking

• US 20080083977A1
• Filed: 04/13/2007
• Published: 04/10/2008
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage
• Granted Patent: US 7,829,438 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

Claims

1. A method of manufacturing a stacked package comprising the steps of:

aligning saw lanes of a first wafer with saw lanes of a second wafer such that the saw lanes of one wafer are positioned above the saw lanes of the other wafer, each of the first and second wafers including a plurality of microelectronic elements attached together at the saw lanes, each microelectronic element having a plurality of traces extending toward the saw lanes;

forming a plurality of openings aligned with the saw lanes of the first wafer and the second wafer, each opening exposing a single trace of at least one microelectronic element; and

electrically connecting leads with at least some of the exposed plurality of traces.

2. The method as claimed in claim 1, wherein at least some of the openings expose a single trace of at least one microelectronic element of the first wafer and a single trace of at least one microelectronic element of the second wafer.

3. The method as claimed in claim 2, further comprising attaching the first wafer to the second wafer after the saw lanes of the two wafers are aligned.

4. The method as claimed in claim 1, wherein the leads include first ends overlying a face of one of the first and the second wafers.

5. The method as claimed in claim 4, wherein the first ends of the leads include conductive bumps.

6. The method as claimed in claim 1, further comprising severing the first and the second wafers along the saw lanes into a plurality of assemblies, each assembly including a plurality of stacked microelectronic elements and exposed leads.

7. The method as claimed in claim 1, further comprising aligning the saw lanes of at least one additional wafer including a plurality of additional microelectronic elements attached together at the saw lanes with the saw lanes of the first and second wafers, the plurality of microelectronic elements having additional traces extending towards the saw lanes, wherein single ones of the additional traces of at least one of the additional microelectronic elements are exposed during the step of forming the openings.

8. A stacked microelectronic assembly comprising:

a first stacked subassembly and a second stacked subassembly overlying a portion of the first stacked subassembly, each stacked subassembly including at least a first microelectronic element having a face and a second microelectronic element having a face overlying and parallel to a face of the first microelectronic element, each of the first and second microelectronic elements having edges extending away from the respective face and a plurality of traces at the respective face extending about at least one respective edge, each of the first and second stacked subassemblies including contacts connected to at least some of the plurality of traces; and

bond wires conductively connecting the contacts of the first stacked subassembly with the contacts of the second stacked subassembly.

9. A stacked microelectronic assembly as claimed in claim 8, wherein each of the first and second subassemblies has a face, at least some of the plurality of contacts being exposed at least one of the faces of the first and second subassemblies.

10. A stacked microelectronic assembly as claimed in claim 8, wherein each of the first and second stacked subassemblies has a face and an edge extending away from the face, wherein the face of the first stacked subassembly extends beyond the face of the second stacked subassembly such that contacts at the face of the first stacked subassembly are exposed beyond the face of the second stacked subassembly.

11. A stacked microelectronic package comprising:

a plurality of subassemblies including a first subassembly and a second subassembly underlying the first subassembly, each subassembly having a front face and a rear face remote from the front face, the front face of the second subassembly confronting the rear face of the first subassembly, each of the first and second subassemblies including a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge, the second subassembly having a plurality of rear contacts exposed at the rear face and a plurality of rear traces extending from the rear contacts about the at least one edge to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

12. The stacked microelectronic package as claimed in claim 11, wherein each of the plurality of subassemblies includes at least one microelectronic chip.

13. An assembly including the stacked microelectronic package as claimed in claim 12, further comprising a circuit panel having terminals conductively connected to at least some package contacts selected from the group consisting of the rear contacts of the second subassembly and front contacts of one subassembly of the plurality of subassemblies.

14. An assembly as claimed in claim 13, further comprising an additional microelectronic chip joined to the stacked microelectronic package such that a face of the additional microelectronic chip confronts a face of one of the first and second subassemblies.

15. An assembly as claimed in claim 14, wherein contacts of the additional microelectronic chip are wire-bonded to the front contacts of the one subassembly.

16. An assembly as claimed in claim 15, further comprising conductive masses joining the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

17. An assembly as claimed in claim 14, wherein the additional microelectronic chip includes a microcontroller.

18. An assembly as claimed in claim 14, wherein at least one of the microelectronic chips in the plurality of subassemblies is replaceable by the additional microelectronic chip by disconnecting the at least one microelectronic chip from ones of the front contacts of the one subassembly and connecting the additional microelectronic chip to the ones of the front contacts.

19. An assembly as claimed in claim 14, further comprising bond wires, the bond wires conductively connecting the front contacts of the one subassembly to the terminals of the circuit panel.

20. An assembly as claimed in claim 19, further comprising conductive masses joining the contacts of the additional microelectronic chip to the front contacts of the one subassembly.

21. An assembly as claimed in claim 14, further comprising bond wires, the bond wires conductively connecting contacts of the additional microelectronic chip to the terminals of the circuit panel.

22. An assembly as claimed in claim 13, further comprising conductive masses joining the terminals of the circuit panel to the exposed front contacts of the one subassembly.

23. An assembly as claimed in claim 22, further comprising an additional microelectronic chip joined to the rear face of the second subassembly, the additional microelectronic chip having contacts conductively connected to terminals of the circuit panel.

24. An assembly as claimed in claim 23, further comprising bond wires, the bond wires joining the contacts of the additional microelectronic chip to the terminals of the circuit panel.

25. An assembly as claimed in claim 13, further comprising conductive masses joining the terminals of the circuit panel to the rear contacts of the second subassembly.

26. An assembly as claimed in claim 25, further comprising an additional microelectronic chip having contacts in conductive communication with the front contacts of the one subassembly.