SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE
First Claim
1. A semiconductor memory device comprising:
- a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first memory cell block includes a first word line coupled to a first row of memory cells on the first semiconductor layer, wherein the second memory cell block includes a second word line coupled to a second row of memory cells on the second semiconductor layer, and wherein the first word line is between the first and second semiconductor layers;
a first row decoder adjacent the memory cell array wherein the first row decoder is configured to control the first word line;
a second row decoder adjacent the memory cell array wherein the second row decoder is configured to control the second word line;
a first wiring electrically connecting the first row decoder and the first word line; and
a second wiring electrically connecting the second row decoder and the second word line.
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Accused Products
Abstract
A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
55 Citations
23 Claims
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1. A semiconductor memory device comprising:
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a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first memory cell block includes a first word line coupled to a first row of memory cells on the first semiconductor layer, wherein the second memory cell block includes a second word line coupled to a second row of memory cells on the second semiconductor layer, and wherein the first word line is between the first and second semiconductor layers; a first row decoder adjacent the memory cell array wherein the first row decoder is configured to control the first word line; a second row decoder adjacent the memory cell array wherein the second row decoder is configured to control the second word line; a first wiring electrically connecting the first row decoder and the first word line; and a second wiring electrically connecting the second row decoder and the second word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor memory device comprising:
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a memory cell array including a memory cell block, wherein the memory cell block includes a first word line coupled to a first row of memory cells and a second word line coupled to a second row of memory cells, and wherein the first word line is between the first and second semiconductor layers; an odd row decoder adjacent the memory cell array wherein the odd row decoder is configured to control the first word line; an even row decoder adjacent the memory cell array wherein the even row decoder is configured to control the second word line wherein the memory cell array is between the odd and even row decoders; a first wiring electrically connecting the odd row decoder and the first word line; and a second wiring electrically connecting the even row decoder and the second word line.
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23. A semiconductor memory device comprising:
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a memory cell array including first and second memory cell blocks on respective first and second semiconductor layers, wherein the first memory cell block includes a first word line coupled to a first row of memory cells on the first semiconductor layer, wherein the second memory cell block includes a second word line coupled to a second row of memory cells on the second semiconductor layer, and wherein the first word line is between the first and second semiconductor layers; a row decoder adjacent the memory cell array wherein the row decoder is configured to control the first and second word lines; and a wiring electrically connecting the first and second word lines and electrically connecting the first and second word lines with the row decoder.
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Specification