Memory system and method for operating a memory system

• US 20080084769A1
• Filed: 10/06/2006
• Published: 04/10/2008
• Est. Priority Date: 10/06/2006
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG, Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG, Qimonda AG (Infineon Technologies AG)
• Inventors: RaghuRam, Siva, Djordjevic, Srdjan
• Application Number:
  US11/544,537
• Publication Number:
  US 20080084769A1
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

A memory system, in particular a buffered memory system, e.g. a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. In one embodiment, the memory system includes at least one buffered memory module, and a device for generating a first and second chip select signal from one single chip select signal. Further, a device for use with a memory system is provided, generating a second number of chip select signals from a first number of chip select signals, the first number of chip select signals being smaller, than the second number of chip select signals.

Claims

1. A memory system, comprising:

at least one buffered memory module; and

a device for generating at least a first and a second chip select signal, and a third and a fourth chip select signal from one single chip select signal and an additional single chip select signal.

2. The memory system of claim 1, the buffered memory module comprising:

a first rank of RAMs selectable with the first chip select signal;

a second rank of RAMs selectable with the second chip select signal, a third rank of RAMs selectable with the third chip select signal, and a fourth rank of RAMs selectable with the fourth chip select signal.

3. The memory system of claim 2, comprising where the single chip select signal and the additional single chip select signal, or a first and a second signal from which the single and the additional single chip select signals are generated are configured to enable or disable selection of the first rank of RAMs, the second rank of RAMs, the third rank of RAMs, or the fourth rank of RAMs in a rank selection enabling/disabling phase of the memory system.

4. The memory system of claim 3, in which the single chip select signal and the additional single chip select signal, or the first and the second signals are adapted to select in a rank selecting phase of the memory system a rank of RAMs enabled for selection in the rank selection enabling/disabling phase of the memory system.

5. The memory system of claim 1, wherein the at least one buffered memory module comprises at least one RAM.

6. The memory system of claim 5, wherein the at least one buffered memory module comprises at least one DRAM.

7. The memory system of claim 1, wherein the at least one memory module comprises at least one buffer component.

8. The memory system of claim 1, configured to comprise a variably adjustable number of memory modules.

9. The memory system of claim 1, additionally comprising a memory controller connected with the at least one buffered memory module via a first bus.

10. The memory system of claim 9, wherein the at least one buffered memory module is connected with a further buffered memory module via a second bus.

11. The memory system of claim 10, wherein the at least one and the further buffered memory module each comprise at least one DRAM, the DRAM of the at least one buffered memory module being connected with a buffer component of the at least one buffered memory module via a third bus, and the DRAM of the further buffered memory module being connected with a buffer component of the further buffered memory module via a fourth bus.

12. A method for operating a memory system, the memory system comprising at least one memory module, the method comprising:

generating a first and a second chip select signal from one single chip select signal; and

generating a third and a fourth chip select signal from an additional single chip select signal.

13. The method of claim 12, comprising generating the first chip select signal for selecting a first rank of RAMs.

14. The method of claim 13, comprising generating the second chip select signal for selecting a second rank of RAMs.

15. The method of claim 14, comprising generating the third chip select signal for selecting a third rank of RAMs.

16. The method of claim 15, comprising the fourth chip select signal for selecting a fourth rank of RAMs.

17. The method of claim 12, comprising wherein in a rank selection enabling/disabling phase of the memory module the single chip select signal is brought in a first state, and the additional single chip select signal is brought in a first state for enabling selection of a first and a second rank of RAMs, and for disabling selection of a third and fourth rank of RAMs.

18. The method of claim 17, comprising wherein in the rank selection enabling/disabling phase the single chip select signal is brought in a second state, different from the first state of the single chip select signal, and the additional single chip select signal is brought in a second state, different from the first state of the additional single chip select signal for disabling selection of the first and the second rank of RAMs, and for enabling selection of the third and the fourth rank of RAMs.

19. A device for use with a memory system, comprising:

where the device is configured for generating a second number of chip select signals from a first number of chip select signals, the first number of chip select signals being smaller, than the second number of chip select signals.

20. The device of claim 19, the second number of chip select signals being bigger than 1.

21. The device of claim 19, the second number of chip select signals being bigger than 3.

22. The device of claim 21, the second number of chip select signals being 4.

23. The device of claim 19, the second number of chip select signals being bigger than 5.

24. A device for use with a memory system, comprising:

where the device is configured for generating a second number of control signals from a first number of control signals, the first number of control signals being smaller, than the second number of control signals.

25. A memory system, comprising:

at least one buffered memory module, the buffered memory module comprising;

a buffer component; and

a device for generating at least a first and a second chip select signal from one single chip select signal.

26. A memory system, comprising:

at least one buffered memory module; and

means for generating at least a first and a second chip select signal, and a third and a fourth chip select signal from one single chip select signal and an additional single chip select signal.