Methods and systems for accessing memory

• US 20080084773A1
• Filed: 10/04/2006
• Published: 04/10/2008
• Est. Priority Date: 10/04/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mcadams, Hugh P., Lin, Sung-Wei, Madan, Sudhir Kumar
• Granted Patent: US 7,630,257 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 2207/229 Timing of a write operation

Abstract

One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Claims

1. A method for accessing a memory device, comprising:

during a read operation in the memory device providing one data value on a local IO line while applying a constant voltage to a complimentary local IO line that is associated with the local IO line; and

during a write operation, providing another data value on the local IO line and providing a complimentary data value on the complimentary local IO line.

2. The method of claim 1, further comprising:

during the read operation, selectively transferring the one data value on the local IO line to a global IO line.

4. The method of claim 1, wherein during the read operation inactivating the complimentary local IO line comprises:

discarding any signal on the complimentary local IO line.

5. The method of claim 1, wherein providing the one data value comprises transferring the data value onto the local IO line via a sense amp.

6. The method of claim 5, wherein during the read operation the sense amp transfers the data value onto the local IO line by coupling the sense amp to the local IO line.

7. The method of claim 5, wherein during the read operation the sense amp transfers the data value on the local IO line by coupling the sense amp to the local IO line while the complimentary local IO line is decoupled from the sense amp.

8. The method of claim 1, wherein the memory device is a ferro-electric memory.

3. (canceled)

9. A sensing system for a memory device, comprising:

a sensing circuit associated with a pair of complimentary local IO lines and a memory cell, wherein the sensing circuit comprises a local IO select circuit that facilitates data transfer between the pair of complimentary local IO lines and the memory cell; and

a global IO select circuit coupled to the pair of complimentary local IO lines and at least one global IO line, the global IO select circuit operable to selectively transfer data from the at least one global IO line to the complimentary local IO lines;

wherein the sensing system is configured to selectively inactivate one of the pair of complimentary local IO lines during a read operation.

10. The system of claim 9, wherein inactivating one of the pair of complimentary local IO lines comprises holding the one of the complimentary local IO lines at a constant voltage during the transfer of data between the one of the complimentary local IO lines and a corresponding global IO line.

11. The system of claim 10, wherein inactivating one of the pair of complimentary local IO lines comprises discarding any signal on the one of the complimentary local IO lines during the transfer of data between the one of the complimentary local IO lines and a corresponding global IO line.

12. The system of claim 9, wherein the memory device is a ferro-electric memory.

13. The system of claim 9, further comprising:

a sense amp connection circuit coupled to the memory cell and the sensing circuit, the sense amp connection circuit configured to selectively couple the sensing circuit to the memory cell.

14. The system of claim 9, wherein the global IO select circuit is coupled to more than one sensing circuit via the one of the complimentary local IO lines.

15. A method for accessing memory comprising:

during a write operation;

providing complementary data to first and second global IO lines, respectively, and transferring the complementary data to first and second local IO lines. respectively, via a first coupling circuit; and

during a read operation;

transferring a data value from the first local IO line to the first global IO line via a transfer circuit while holding at least one of;

the second global IO line and the second local IO line at an approximately constant voltage.

18. The method of claim 15, wherein the first and second local IO lines and the first and second global IO lines are associated with a plurality of memory cells.

19. The method of claim 18, further comprising:

during the read operation coupling a sensing circuit to the first local IO line to transfer the data.

20. The method of claim 19, further comprising:

during the read operation and prior to coupling the sensing circuit to the first local IO line, coupling the sensing circuit to one of the plurality of memory cells to provide the data.

21. The method of claim 18, further comprising:

during the read operation coupling the sensing circuit to a memory cell to provide the data to the sensing circuit.

22. The method of claim 21, further comprising:

during the read operation after coupling the sense circuit to a memory cell to provide the data, transferring the data from the sensing circuit to the local IO line.

23. The method of claim 15, wherein the memory device is a ferro-electric memory.

16. (canceled)

17. (canceled)

24. A method for accessing memory comprising:

during a write operation;

transferring one data value from a first global IO line to first and second local IO lines, wherein the first and second local IO lines comprise a pair of complimentary local IO lines; and

during a read operation;

transferring another data value from the first local IO line to the first global IO line while the second local IO line is held at an approximately constant voltage,

26. The method of claim 24 wherein the first and second local IO lines and the first global IO line are associated with a plurality of memory cells.

27. The method of claim 26, further comprising:

during the read operation, transferring the one data value from a sensing circuit to the first local IO line.

28. The method of claim 27, further comprising:

during the read operation and prior to transferring the one data value from the sensing circuit to the first local IO line, coupling the sensing circuit to a memory cell to provide the one data value.

29. The method of claim 24, wherein the memory device is a ferro-electric memory.

25. (canceled)