DISTRIBUTED MICRO INSTRUCTION SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING

• US 20080084850A1
• Filed: 08/20/2007
• Published: 04/10/2008
• Est. Priority Date: 07/24/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Chou, Paul, Chen, Song, Rieken, Keith, Balasubramonian, Venugopal, Woodthorpe, Christopher
• Granted Patent: US 8,014,786 B2
• Time in Patent Office: Days
• US Class Current: 370/335
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/462 with multiple register sets
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

Claims

1. A wireless communication system for hosting a plurality of processes, each process in said plurality of processes executed in accordance with a communication protocol, the communication protocol including a set of functions, said wireless communication system comprising:

a plurality of application specific instruction set processors (ASISPs), each ASISP capable of executing a subset of said set of functions included in said communication protocol; and

a scheduler connected to said plurality of ASISPs for scheduling said plurality of ASISPs in accordance with a time-slicing algorithm so that each process in said plurality of processes is supported by said wireless communication system.

2. The wireless communication system of claim 1 wherein each said ASISP in said plurality of ASISPs further comprises:

an input register for receiving an input program and state associated with a process in said plurality of processes, each instruction in said input program being part of a limited purpose instruction set that supports said subset of functions included in said communication protocol; and

an output register for storing a value that indicates a state of said process after execution of said input program.

3. The wireless communication system of claim 2, wherein

said input program is associated with a first process selected from said plurality of processes;

and

said time-slicing algorithm includes a step of allocating a selected ASISP in said plurality of ASISPs to said input program for a predetermined period of time.

4. The wireless communication system of claim 3 wherein said input program is not interrupted by said scheduler during said predetermined period of time.

5. The wireless communication system of claim 3 wherein execution of said input program is completed during said predetermined period of time.

6. The wireless communication system of claim 2, wherein said scheduler further includes a synchronization mechanism for synchronizing said plurality of ASISPs, the synchronization mechanism capable of reallocating an ASISP in said plurality of ASISPs from a first input program that is associated with a first process to a second input program that is associated with a second process.

7. The wireless communication system of claim 6 wherein said first process is a first echo and said second process is a second echo.

8. The wireless communication system of claim 6 wherein said first process is each echo associated with a first mobile and said second process is each echo associated with a second mobile.

9. The wireless communication system of claim 2, wherein

said time-slicing algorithm defines a predetermined period of time;

said limited purpose instruction set includes a “

wait”

instruction for synchronization; and

each ASISP in said plurality of ASISPs is configured so that when said “

wait”

instruction is received by said input register, the ASISP does execute a communication protocol function during said predetermined period of time and then automatically returns to an idle state thereby reducing a power consumption of the ASISP during the predetermined period of time.

10. The wireless communication system of claim 2, further including a plurality of memory modules, each memory module in said plurality of memory modules associated with a different ASISP selected from said plurality of ASISPs.

11. The wireless communication system of claim 10 wherein said state of said process stored in said output register is stored in a unique segment of said different memory module, the unique segment of said memory module being determined by an identity of said process.

12. The wireless communication system of claim 11 wherein said output register is further used to store a process identifier value that provides said identity of said process.

13. The wireless communication system of claim 1 wherein said communication protocol is a code division multiple access (CDMA) protocol.

14. The wireless communication system of claim 13 wherein said communication protocol is selected from the group consisting of IS-95 CDMA, IS-95B CDMA, CDMA TIA IS2000, TIA IS 2000A, wideband CDMA (WCDMA), cdma2000, and ARIB WCDMA.

15. The wireless communication system of claim 1 wherein said communication protocol is a time division multiple access (TDMA) protocol.

16. The wireless communication system of claim 15 wherein said communication protocol is IS-136 TDMA.

17. The wireless communication system of claim 1 wherein said ASISP is a finger ASISP and said subset of functions comprises a delay lock loop (DLL) and a channel estimation.

18. The wireless communication system of claim 1 wherein said ASISP is a combiner ASISP and said subset of functions comprises a frequency error estimation, a finger energy estimation, and a signal-to-interference (SIR) estimation.

19. The wireless communication system of claim 1 wherein each process in said plurality of processes is an echo.

20. The wireless communication system of claim 1 wherein each process in said plurality of processes uniquely corresponds to a different mobile hosted by said wireless communication system and each said process combines a plurality of echoes associated with the corresponding different mobile.

21-47. -47. (canceled)