EXCHANGE NODE AND EXCHANGE NODE CONTROL METHOD

• US 20080084898A1
• Filed: 09/16/2005
• Published: 04/10/2008
• Est. Priority Date: 10/14/2004
• Status: Active Grant

• Current Assignee: Tokyo Denki University
• Original Assignee: Tokyo Denki University
• Inventors: Miyahara, Kazunori, Miyaho, Noriharu
• Granted Patent: US 7,760,625 B2
• Time in Patent Office: Days
• US Class Current: 370/498
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 43/0882 Utilisation of link capacity
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/12 Avoiding congestion; Recovering from congestion
• CPC Class Codes: H04L 47/2408 for supporting different services, e.g. a differentiated services [DiffServ] type of service
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced.

The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10. More preferably, a frame compression circuit 16, a frame decompression circuit 18 and a priority determination circuit 20 are arranged.

Claims

1. An exchange node comprising:

an input buffer unit for writing input data which is connection type packet data to a shift register and outputting input buffer data at completion of the writing of the input data;

a distribution unit, which is input with the input buffer data from the input buffer unit, for outputting the input buffer data from the input buffer unit as priority control processing data by a priority control signal indicating that the input data input to the input buffer unit is priority control processing data;

an identification unit for identifying the priority control signal contained in the input data input to the input buffer unit, and outputting the priority control signal to the distribution unit;

a time slot allocation circuit for obtaining time slot information indicating that a time slot for writing the priority control processing data is unused, and outputting a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a multiplexing circuit for writing the priority control processing data from the distribution unit to the shift register allocated by the time slot specifying signal from the time slot allocation circuit, and outputting multiplexed data at completion of the writing of the priority control processing data; and

an output/distribution unit for transmitting the multiplexed data from the multiplexing circuit to an outgoing line and outputting information of the unused time slot of the multiplexed data from the multiplexing circuit to the time slot allocation circuit as time slot information.

3. The exchange node according to claim 1 or 2, further comprising a priority determination circuit for detecting priority contained in the priority control processing data and outputting priority information to the time slot allocation circuit, wherein

the time slot allocation circuit specifies a time slot according to the priority of the priority information.

4. The exchange node according to claim 1, 2 or 3, further comprising a priority determination circuit for detecting priority contained in the priority control processing data and outputting priority information to the time slot allocation circuit, wherein

the time slot allocation circuit varies the number of time slot to be specified according to the priority of the priority information.

5. The exchange node according to claim 1, 2, 3, or 4, wherein

the multiplexing circuit includes a plurality of shift registers which can perform parallel processing.

6. The exchange node according to claim 1, 2, 3, 4, or 5, wherein

the time slot allocation circuit specifies the time slot according to the priority with respect to the priority control processing data containing the priority information of two or more stages.

7. The exchange node according to claim 1, 2, 3, 4, 5 or 6, wherein

the time slot allocation circuit specifies the number of time slots according to the length of the priority control processing data.

8. The exchange node according to claim 1, 2, 3, 4, 5, 6 or 7, wherein

the time slot allocation circuit outputs the time slot specifying signal specifying the time slot for every connection.

9. The exchange node according to claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein

the time slot allocation circuit specifies the time slot regardless of communication speed of a transmission path for transmitting the input data to the input buffer unit.

10. The exchange node according to claim 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein

the time slot allocation circuit outputs a “

time-series order”

of each time slot to the multiplexing circuit as “

time-series order”

of time slot signal when specifying a plurality of time slots for the priority control processing data; and

the multiplexing circuit writes the priority control processing data in the order of the “

time-series order”

of time slot signal.

11. The exchange node according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein

the time slot allocation circuit resets specification of the time slot after a predetermined time has elapsed after specifying the time slot.

12. The exchange node according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein

the time slot allocation circuit resets specification of the time slot by a priority control release signal contained in the priority control signal after specifying the time slot.

13. The exchange node according to claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein

the time slot allocation circuit resets specification of the time slot by writing another packet data to the input buffer unit after specifying the time slot.

27. The exchange node according to any one of claims 1 to 13, further comprising a connectionless type data allocation circuit for allocating a time slot of connectionless type packet data and outputting a time slot specifying signal to the multiplexing circuit, wherein

the distribution unit outputs the header information of the connectionless type data to the connectionless data allocation circuit when the input data input to the input buffer unit is the connectionless type packet data;

and

the multiplexing circuit further multiplexes the connectionless type packet data on the multiplexed data.

2. An exchange node comprising:

an input buffer unit for writing input data which is connection type packet data to a shift register and outputting input buffer data at completion of the writing of the input data;

a distribution unit, which is input with the input buffer data from the input buffer unit, for outputting the input buffer data from the input buffer unit as priority control processing data by a priority control signal indicating that the input data input to the input buffer unit is priority control processing data;

an identification unit for identifying the priority control signal contained in the input data input to the input buffer unit, and outputting the priority control signal to the distribution unit;

a time slot allocation circuit for obtaining time slot information indicating that a time slot for writing the priority control processing data is unused, and outputting a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a frame compression circuit, which is input with the priority control processing data from the distribution unit, for compressing time width of the priority control processing data and outputting compressed data;

a multiplexing circuit for writing the compressed data from the frame compression unit to the shift register allocated by the time slot specifying signal from the time slot allocation circuit, and outputting multiplexed data at completion of the writing of the compressed data;

a frame decompression circuit, which is input with the multiplexed data from the multiplexing circuit, for decompressing the time width of the multiplexed data and outputting decompressed data; and

an output/distribution unit for transmitting the decompressed data from the frame decompression circuit to an outgoing line and outputting information of the unused time slot of the decompressed data from the frame decompression circuit to the time slot allocation circuit as time slot information.

14. An exchange node control method comprising the steps of:

an input step in which an input buffer unit writes input data which is connection type packet data to a shift register and outputs input buffer data at completion of the writing of the input data;

a distribution step in which a distribution unit, which is input with the input buffer data output in the input step, outputs the input buffer data output in the input step as priority control processing data by a priority control signal indicating that the input data input in the input step is priority control processing data;

an identification step in which an identification unit identifies the priority control signal contained in the input data input in the input step, and outputs the priority control signal to the distribution unit;

a time slot allocation step in which a time slot allocation circuit obtains time slot information indicating that a time slot for writing the priority control processing data is unused, and outputs a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a multiplexing step in which a multiplexing circuit writes the priority control processing data output in the distribution step to the shift register allocated by the time slot specifying signal output in the time slot allocation step, and outputs multiplexed data at completion of the writing of the priority control processing data; and

an output step in which an output/distribution unit transmits the multiplexed data output in the multiplexing step to an outgoing line and outputs information of the unused time slot of the multiplexed data output in the multiplexing step to the time slot allocation circuit as time slot information.

16. The exchange node control method according to claim 14 or 15, further comprising a priority determination step in which a priority determination circuit detects priority contained in the priority control processing data and outputs priority information to the time slot allocation circuit, wherein

the time slot allocation circuit specifies a time slot according to the priority of the priority information in the time slot allocation step.

17. The exchange node control method according to claim 14, 15 or 16 further comprising a priority determination step in which a priority determination circuit detects priority contained in the priority control processing data and outputs priority information to the time slot allocation circuit, wherein

the time slot allocation circuit varies the number of time slots according to the priority of the priority information in the time slot allocation step.

18. The exchange node control method according to claim 14, 15, 16 or 17, wherein the multiplexing step includes a step in which the multiplexing circuit writes data to a plurality of shift registers which can perform parallel processing.

19. The exchange node control method according to claim 14, 15, 16, 17 or 18, wherein

the time slot allocation circuit specifies the time slot according to the priority with respect to the priority control processing data containing the priority information of two or more stages in the time slot allocation step.

20. The exchange node control method according to claim 14, 15, 16, 17, 18 or 19, wherein

the time slot allocation circuit specifies the number of time slots according to the length of the priority control processing data in the time slot allocation step.

21. The exchange node control method according to claim 14, 15, 16, 17, 18, 19 or 20, wherein

the time slot allocation circuit outputs the time slot specifying signal specifying the time slot for every connection in the time slot allocation step.

22. The exchange node control method according to claim 14, 15, 16, 17, 18, 19, 20, or 21, wherein

the time slot allocation circuit specifies the time slot regardless of communication speed when the input data is input to the input buffer unit in the time slot allocation step.

23. The exchange node control method according to claim 14, 15, 16, 17, 18, 19, 20, 21, or 22, wherein

the time slot allocation circuit outputs a “

time-series order”

of each time slot to the multiplexing circuit as “

time-series order”

of time slot signal when specifying a plurality of time slots for the priority control processing data in the time slot allocation step; and

the multiplexing circuit writes the priority control processing data in the order of the “

time-series order”

of time slot signal.

24. The exchange node control method according to claim 14, 15, 16, 17, 18, 19, 20, 21, 22 or 23, wherein

the time slot allocation circuit resets specification of the time slot after a predetermined time has elapsed after specifying the time slot in the time slot allocation step.

25. The exchange node control method according to claim 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 or 24, wherein

the time slot allocation circuit resets specification of the time slot by a priority control release signal contained in the priority control signal after specifying the time slot in the time slot allocation step.

26. The exchange node control method according to claim 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 or 25, wherein

the time slot allocation circuit resets specification of the time slot by writing another packet data to the input buffer unit after specifying the time slot in the time slot allocation step.

15. An exchange node control method comprising the steps of:

an input step in which an input buffer unit writes input data which is connection type packet data to a shift register and outputs input buffer data at completion of the writing of the input data;

a distribution step in which a distribution unit, which is input with the input buffer data output in the input step, outputs the input buffer data output in the input step as priority control processing data by a priority control signal indicating that the input data input in the input step is priority control processing data;

an identification step in which an identification unit identifies the priority control signal contained in the input data input in the input step, and outputs the priority control signal to the distribution unit;

a time slot allocation step in which a time slot allocation circuit obtains time slot information indicating that a time slot for writing the priority control processing data is unused, and outputs a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a frame compression step in which a frame compression circuit, which is input with the priority control processing data output in the distribution step, compresses time width of the priority control processing data and outputs compressed data;

a multiplexing step in which a multiplexing circuit writes the compressed data output in the frame compression step to the shift register allocated by the time slot specifying signal output in the time slot allocation step, and outputs multiplexed data at completion of the writing of the compressed data;

a frame decompression step in which a frame decompression circuit, which is input with the multiplexed data output in the multiplexing step, decompresses the time width of the multiplexed data and outputs decompressed data; and

an output step in which an output/distribution unit transmits the decompressed data output in the frame decompression step to an outgoing line and outputs information of the unused time slot of the decompressed data output in the frame decompression step to the time slot allocation circuit as time slot information.

28. An exchange node comprising:

an input buffer unit for writing input data which is connectionless type packet data to a shift register and outputting input buffer data at completion of the writing of the input data;

a distribution unit, which is input with the input buffer data from the input buffer unit, for outputting the input buffer data from the input buffer unit as priority control processing data by a priority control signal indicating that the input data input to the input buffer unit is priority control processing data;

an identification unit for identifying the priority control signal contained in the input data input to the input buffer unit, and outputting the priority control signal to the distribution unit;

a time slot allocation circuit for obtaining time slot information indicating that a time slot for writing the priority control processing data is unused and the priority control signal from the identification unit, and outputting a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a time slot information acquiring unit for outputting information on unused time slot of the time slot specifying signal from the time slot allocation circuit to the time slot allocation circuit as time slot information; and

a multiplexing circuit for writing the priority control processing data from the distribution unit to the shift register allocated by the time slot specifying signal from the time slot allocation circuit, and outputting multiplexed data at completion of the writing of the priority control processing data.

29. The exchange node according to claim 28, further comprising a shift register for storing the priority control processing data output from the distribution unit, and outputting the priority control processing data to the multiplexing circuit when the time slot specifying signal is input from the time slot allocation circuit.

32. The exchange node according to any one of claims 28 to 31, wherein

the time slot allocation circuit outputs the time slot specifying signal to the multiplexing circuit at a constant time from when the input data is input to the input buffer unit, and preferentially allocates the time slot of write destination of the priority control processing data to time slot allocated with the packet identifying information when the priority control signal of the packet identifying information same as the packet identifying information contained in the time slot information is input;

and

the time slot information acquiring unit outputs the information of the unused time slot of the time slot specifying signal from the time slot allocation circuit and the packet identifying information allocated to the time slot to the time slot allocation circuit as time slot information, and erases the packet identifying information allocated to the unused time slot after a constant time set in advance has elapsed.

33. The exchange node according to any one of claims 28 to 31, wherein

the time slot allocation circuit outputs the time slot specifying signal to the multiplexing circuit at a constant time set in advance, stores the already allocated time slot as reserved time slot if the priority control processing data not completed with allocation of the time slot is remaining, specifies the remaining time slot when the priority control signal containing the packet identifying information same as the packet identifying information contained in the priority control processing data allocated with the reserved time slot is input, and completes the allocation of the time slot of the priority control processing data of the priority control signal.

34. The exchange node according to any one of claims 28 to 33, further comprising a non-priority control processing data allocation circuit for allocating a time slot of the non-priority control processing data not requesting for priority control of the input data, and outputting the non-priority control processing data allocated with the time slot, wherein

the distribution unit outputs the input data not requesting for priority control to the non-priority control processing data allocation circuit as non-priority control processing data by a priority control signal indicating that the input data is the priority control processing data;

and

the multiplexing circuit further multiplexes the non-priority control processing data output by the non-priority control processing data allocation circuit on the multiplexed data.

35. The exchange node according to any one of claims 28 to 34, further comprising a connection type data allocation circuit for allocating a time slot of the connection type packet data output from the distribution unit and outputting the packet data allocated with the time slot, wherein

the distribution unit outputs to the connection type data allocation circuit as connection type data when the input data input to the input buffer unit is connection type packet data;

and

the multiplexing circuit further multiplexes the connection type data output by the connection type data allocation circuit on the multiplexed data.

36. The exchange node according to any one of claims 28 to 35, wherein

required time e for each step is calculated as,

$\begin{array}{c}e<\end{array}$

MIN i = 1 , 2 , …





N 

{ B 

( i ) / A 

( i ) } / ( N ×

d ) [ 



1 ]

where number of lines for inputting the input data to the input buffer unit is N, i^th (i is an integer from 1 to N) line speed of the line is A(i), minimum size of the i^th packet data of the line is B (i), and number of execution process until the time slot is allocated by the time slot allocation circuit is d steps.

37. The exchange node according to any one of claims 28 to 36, further comprising a priority determination circuit for detecting the priority contained in the priority control processing data and outputting the priority information to the time slot allocation circuit, wherein

the time slot allocation circuit specifies the time slot according to the priority of the priority information.

38. The exchange node according to any one of claims 28 to 37, further comprising a priority determination circuit for detecting priority contained in the priority control processing data and outputting priority information to the time slot allocation circuit, wherein

the time slot allocation circuit varies the number of time slot to be specified according to the priority of the priority information.

39. The exchange node according to any one of claims 28 to 38, wherein

the multiplexing circuit includes a plurality of shift registers which can perform parallel processing.

40. The exchange node according to any one of claims 28 to 39, wherein

the time slot allocation circuit specifies the time slot according to the priority with respect to the priority control processing data containing the priority information of two or more stages.

41. The exchange node according to any one of claims 28 to 40, wherein

the time slot allocation circuit specifies the number of time slots according to the length of the priority control processing data.

42. The exchange node according to any one of claims 28 to 41, wherein

the time slot allocation circuit specifies the time slot regardless of communication speed of a transmission path for transmitting the input data to the input buffer unit.

43. The exchange node according to any one of claims 28 to 42, wherein

the time slot allocation circuit outputs a “

time-series order”

of each time slot to the multiplexing circuit as “

time-series order”

of time slot signal when specifying a plurality of time slots for the priority control processing data; and

the multiplexing circuit writes the priority control processing data in the order of the “

time-series order”

of time slot signal.

44. The exchange node according to any one of claims 28 to 43, wherein

the time slot allocation circuit resets specification of the time slot after a predetermined time has elapsed after specifying the time slot.

45. The exchange node according to any one of claims 28 to 44, wherein

the time slot allocation circuit resets specification of the time slot by a priority control release signal contained in the priority control signal after specifying the time slot.

46. The exchange node according to any one of claims 28 to 45, wherein

the time slot allocation circuit resets specification of the time slot by writing another packet data to the input buffer unit after specifying the time slot.

47. The exchange node according to any one of claims 28 to 46, further comprising:

a plurality of multiplexing circuits;

a plurality of distributors, connected to a plurality of outgoing lines, for distributing the multiplexed data output from each multiplexing circuit for each outgoing line; and

a selector circuit, arranged between the multiplexing circuit and the distributor, for distributing the priority control processing data multiplexed to the multiplexed data to the distributor corresponding to the direction path.

30. An exchange node comprising:

an input buffer unit for writing input data which is connectionless type packet data to a shift register and outputting input buffer data at completion of the writing of the input data;

a distribution unit, which is input with the input buffer data from the input buffer unit, for outputting the input buffer data from the input buffer unit as priority control processing data by a priority control signal indicating that the input data input to the input buffer unit is priority control processing data;

an identification unit for identifying the priority control signal contained in the input data input to the input buffer unit, and outputting the priority control signal to the distribution unit;

a time slot allocation circuit for obtaining time slot information indicating that a time slot for writing the priority control processing data is unused and the priority control signal from the identification unit, and outputting a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a time slot information acquiring unit for outputting information on unused time slot of the time slot specifying signal from the time slot allocation circuit to the time slot allocation circuit as time slot information;

a frame compression circuit, which is input with the priority control processing data from the distribution unit, for compressing time width of the priority control processing data and outputting compressed data;

a multiplexing circuit for writing the compressed data from the frame compression circuit to the shift register allocated by the time slot specifying signal from the time slot allocation circuit, and outputting multiplexed data at completion of the writing of the compressed data; and

a frame decompression circuit, which is input with the multiplexed data from the multiplexing circuit, for decompressing the time width of the multiplexed data and outputting decompressed data.

31. The exchange node according to claim 30, further comprising a shift register for storing the compressed data output from the frame compression unit, and outputting the compressed data to the multiplexing circuit when the time slot specifying signal is input from the time slot allocation circuit.

48. An exchange node control method comprising the steps of:

an input step in which an input buffer unit writes input data which is connectionless type packet data to a shift register and outputs input buffer data at completion of the writing of the input data;

a distribution step in which a distribution unit, which is input with the input buffer data output in the input step, outputs the input buffer data output in the input step as priority control processing data by a priority control signal indicating that the input data input in the input step is priority control processing data;

an identification step in which an identification unit identifies the priority control signal contained in the input data input in the input step, and outputs the priority control signal to the distribution unit;

a time slot allocation step in which a time slot allocation circuit obtains time slot information indicating that a time slot for writing the priority control processing data is unused and the priority control signal from the identification unit, and outputs a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a time slot information acquiring step in which a time slot information acquiring unit outputs information of the unused time slot of the time slot specifying signal output in the time slot allocation step to the time slot allocation circuit as the time slot information; and

a multiplexing step in which a multiplexing circuit writes the priority control processing data output in the distribution step to the shift register allocated by the time slot specifying signal output in the time slot allocation step, and outputs multiplexed data at completion of the writing of the priority control processing data.

50. The exchange node control method according to claim 48 or 49, wherein

the time slot allocation circuit outputs the time slot specifying signal to the multiplexing circuit at a constant time from when the input data is input to the input buffer unit, and preferentially allocates the time slot of write destination of the priority control processing data to time slot allocated with the packet identifying information when the priority control signal of the packet identifying information same as the packet identifying information contained in the time slot information is input in the time slot allocation step;

and

the time slot information acquiring unit outputs the information of the unused time slot of the time slot specifying signal output in the time slot allocation step and the packet identifying information allocated to the time slot to the time slot allocation circuit as the time slot information, and erases the packet identifying information allocated to the unused time slot after a constant time set in advance has elapsed in the time slot information acquiring step.

51. The exchange node control method according to claim 48 or 49, wherein

the time slot allocation circuit outputs the time slot specifying signal to the multiplexing circuit at a constant time set in advance, stores the already allocated time slot as reserved time slot if the priority control processing data not completed with allocation of the time slot is remaining, specifies the remaining time slot when the priority control signal containing the packet identifying information same as the packet identifying information contained in the priority control processing data allocated with the reserved time slot is input, and completes the allocation of the time slot of the priority control processing data of the priority control signal in the time slot allocation step.

52. The exchange node control method according to any one of claims 48 to 51, further comprising a priority determination step in which a priority determination circuit detects priority contained in the priority control processing data and outputs priority information to the time slot allocation circuit, wherein

the time slot allocation circuit specifies a time slot according to the priority of the priority information in the time slot allocation step.

53. The exchange node control method according to any one of claims 48 to 52, further comprising a priority determination step in which a priority determination circuit detects priority contained in the priority control processing data and outputs priority information to the time slot allocation circuit, wherein

the time slot allocation circuit varies the number of time slots according to the priority of the priority information in the time slot allocation step.

54. The exchange node control method according to any one of claims 48 to 53, wherein

the multiplexing step includes a step in which the multiplexing circuit writes data to a plurality of shift registers which can perform parallel processing.

55. The exchange node control method according to any one of claims 48 to 54, wherein

the time slot allocation circuit specifies the time slot according to the priority with respect to the priority control processing data containing the priority information of two or more stages in the time slot allocation step.

56. The exchange node control method according to any one of claims 48 to 55, wherein

the time slot allocation circuit specifies the number of time slots according to the length of the priority control processing data in the time slot allocation step.

57. The exchange node control method according to any one of claims 48 to 56, wherein

the time slot allocation circuit specifies the time slot regardless of communication speed when the input data is input to the input buffer unit in the time slot allocation step.

58. The exchange node control method according to any one of claims 48 to 57, wherein

the time slot allocation circuit outputs a “

time-series order”

of each time slot to the multiplexing circuit as “

time-series order”

of time slot signal when specifying a plurality of time slots for the priority control processing data in the time slot allocation step; and

the multiplexing circuit writes the priority control processing data in the order of the “

time-series order”

of time slot signal.

59. The exchange node control method according to any one of claims 48 to 58, wherein

the time slot allocation circuit resets specification of the time slot after a predetermined time has elapsed after specifying the time slot in the time slot allocation step.

60. The exchange node control method according to any one of claims 48 to 59, wherein

the time slot allocation circuit resets specification of the time slot by a priority control release signal contained in the priority control signal after specifying the time slot in the time slot allocation step.

61. The exchange node control method according to any one of claims 48 to 60, wherein

the time slot allocation circuit resets specification of the time slot by writing another packet data to the input buffer unit after specifying the time slot in the time slot allocation step.

49. An exchange node control method comprising the steps of:

an input step in which an input buffer unit writes input data which is connectionless type packet data to a shift register and outputs input buffer data at completion of the writing of the input data;

a distribution step in which a distribution unit, which is input with the input buffer data output in the input step, outputs the input buffer data output in the input step as priority control processing data by a priority control signal indicating that the input data input in the input step is priority control processing data;

an identification step in which an identification unit identifies the priority control signal contained in the input data input in the input step, and outputs the priority control signal to the distribution unit;

a time slot allocation step in which a time slot allocation circuit obtains time slot information indicating that a time slot for writing the priority control processing data is unused and the priority control signal from the identification unit, and outputs a time slot specifying signal specifying a time slot of write destination of the priority control processing data from the unused time slots;

a time slot information acquiring step in which a time slot information acquiring circuit outputs information of the unused time slot of the time slot specifying signal output in the time slot allocation step to the time slot allocation circuit as the time slot information;

a frame compression step in which a frame compression circuit, which is input with the priority control processing data output in the distribution step, compresses time width of the priority control processing data and outputs compressed data;

a multiplexing step in which a multiplexing circuit writes the compressed data output in the frame compression step to the shift register allocated by the time slot specifying signal output in the time slot allocation step, and outputs multiplexed data at completion of the writing of the compressed data; and

a frame decompression step in which a frame decompression circuit, which is input with the multiplexed data output in the multiplexing step, decompresses time width of the multiplexed data and outputs decompressed data.