Novel Gate Structure with Low Resistance for High Power Semiconductor Devices

• US 20080085591A1
• Filed: 10/06/2006
• Published: 04/10/2008
• Est. Priority Date: 10/06/2006
• Status: Active Grant

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Zhang, Qingchun, Gomez, Mercedes P., Hanna, Emil M., Luo, Wen-Ben
• Granted Patent: US 7,589,377 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66909 Vertical transistors, e.g. tecnetrons
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

Claims

1. A gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device, comprising:

a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region;

a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region;

a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal layer interior region; and

an undoped poly-silicon layer deposited to fill the first metal layer interior region.

2. The gate structure of claim 1, wherein the dielectric layer is composed of a dielectric material selected from the group consisting of silicon-dioxide (SiO₂) and silicon-nitride (Si₃N₄), the dielectric layer having a thickness of between about 0.4 microns to about 0.8 microns.

3. The gate structure of claim 1, wherein the doped poly-silicon layer is composed of a positively doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the doped poly silicon layer having a doping concentration of between about 5×

10¹⁸ cm<sup>−

3</sup> to about 5×

10²⁰ cm<sup>−

3</sup>, the doped poly silicon layer having a thickness of between about 2.0 microns to about 4.0 microns.

4. The gate structure of claim 1, wherein the first metal layer includes molybdenum having a thickness of between about 0.3 microns to about 0.6 microns, the first metal layer being electrically connected to a gate terminal.

5. The gate structure of claim 4, wherein end portions of the side walls of the first metal layer are disposed below the side walls of the dielectric layer a distance of between about 0.5 microns to about 2.0 microns.

6. The gate structure of claim 1, further comprising:

a P+ Junction gate adjacent to a floor portion of the dielectric layer, the P+junction gate being composed of a P-type doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the P+junction gate having a doping concentration of between about 1×

10¹⁸ cm<sup>−

3</sup> and 5×

10¹⁸ cm<sup>−

3</sup>, the P+junction gate being one of blanket doped and locally doped, the P+junction gate having thickness from about 0.2 microns to about 0.5 microns.

7. The gate structure of claim 6, further comprising:

a drift region surrounding the dielectric layer and the P+ Junction gate.

8. The gate structure of claim 7, further comprising a drain terminal adjacent to the drift region on a side opposite the P+ Junction gate, the drain terminal comprising a second metal layer consisting of a metal selected from the group consisting of aluminum (Al) and nickel (Ni).

9. The gate structure of claim 1, further comprising a source terminal adjacent to the dielectric layer on a side facing the dielectric layer interior region, the source terminal comprising a third metal layer consisting of a metal selected from the group consisting of aluminum (Al) and nickel (Ni).

10. The gate structure of claim 8, further comprising a cap layer disposed between the source terminal and the undoped poly-silicon layer, the cap layer consisting of a material selected from the group consisting of silicon dioxide (SiO2) and undoped poly-silicon, the cap layer having a thickness of between about 0.5 microns to about 2.0 microns.

11. The gate structure of claim 9, further comprising:

a first conduction channel disposed adjacent to the dielectric layer and between the source terminal and the drift region,

wherein the first conduction channel comprises;

a first N+ doped region having a first surface, a second surface, a first end, and a second end;

a first P-channel region having a first surface, a second surface, a first end, and a second end;

a first P+ doped region having a first surface, a second surface, a first end, and a second end,

wherein the first N+ doped region first surface is adjacent to the source terminal, the N+ doped region second end is adjacent to the dielectric layer where the dielectric layer meets the source terminal, the N+ doped region second surface is adjacent to the P-channel first surface, the P-channel second surface is adjacent to the drift region, the P-channel second end is adjacent to the dielectric layer, the P+ doped region first surface is adjacent to the source terminal, the N+ doped region first end, and the P-channel first end, and the P+ doped region second surface is adjacent to the drift region.

12. The gate structure of claim 10, further comprising:

a second conduction channel disposed adjacent to the dielectric layer and between the source terminal and the drift region in a position opposite the first conduction channel,

wherein the second conduction channel comprises;

a N+ doped region having a first surface, a second surface, a first end, and a second end;

a P-channel region having a first surface, a second surface, a first end, and a second end;

a P+ doped region having a first surface, a second surface, a first end, and a second end,

wherein the N+ doped region first surface is adjacent to the source terminal, the N+ doped region second end is adjacent to the dielectric layer where the dielectric layer meets the source terminal, the N+ doped region second surface is adjacent to the P-channel first surface, the P-channel second surface is adjacent to the drift region, the P-channel second end is adjacent to the dielectric layer, the P+ doped region first surface is adjacent to the source terminal, the N+ doped region first end, and the P-channel first end, and the P+ doped region second surface is adjacent to the drift region.

13. A method using a UMOS transistor,

the UMOS transistor comprising:

a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region;

a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region, the doped poly-silicon layer having side walls and a floor surrounding a doped poly-silicon layer interior region, the doped poly-silicon layer is composed of a positively doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC);

a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer, the first metal layer having side walls and a floor surrounding a first metal layer interior region, the side walls of the first metal layer being etched below the side walls of the dielectric layer, the first metal layer being electrically connected to a gate terminal, the side walls of the first metal layer being etched below the side walls of the dielectric layer a distance of between about 0.5 microns to about 2.0 microns;

an undoped poly-silicon layer deposited to fill the metal layer interior region, the undoped poly-silicon layer being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC);

a P+ Junction gate adjacent to-a floor portion of the dielectric layer;

a drift region surrounding the dielectric layer and the P+ Junction gate;

a drain terminal adjacent to the drift region on a side opposite the P+ Junction gate;

a source terminal adjacent to the dielectric layer on a side facing the dielectric layer interior region, the method of using the UMOS transistor comprising the operation of;

applying a controlling voltage to the gate terminal, the controlling voltage applied to the gate terminal being effective in controlling the flow of electrical current between the source terminal and the drain terminal.

14. The method of claim 13, wherein the dielectric layer is composed of a dielectric material selected from the group consisting of silicon-dioxide (SiO₂) and silicon-nitride (Si₃N₄) the dielectric layer having a thickness of between about 0.4 microns to about 0.8 microns.

15. The method of claim 13, wherein the metal layer includes molybdenum having a thickness of between about 0.3 microns to about 0.6 microns, the metal layer comprising a gate terminal.

16. The method of claim 13, wherein the doped poly-silicon layer is composed of a positively doped semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC), the doped poly silicon layer having a doping concentration of between about 5×

10¹⁸ cm<sup>−

3</sup> to about 5×

10²⁰ cm<sup>−

3</sup>, the doped poly silicon layer having a thickness of between about 2.0 microns to about 4.0 microns.

17. A gate structure for a Junction Field Effect Transistor (JFET) device, comprising:

a dielectric layer having two disjoint sidewall regions deposited on side walls of a trench having side walls and a floor, each disjoint side wall region having a first side facing into a trench interior region and a second side facing away from the trench interior region;

a metal layer formed into a U-shape deposited on the dielectric layer first sides and the floor of the of the trench surrounding a metal layer interior region, the metal layer being electrically connected to a gate terminal;

an undoped poly-silicon layer deposited to fill the metal layer interior region, the undoped poly-silicon layer being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC).

18. The gate structure of claim 17, wherein the dielectric layer is composed of a dielectric material selected from the group consisting of silicon-dioxide (SiO₂) and silicon-nitride (Si₃N₄), the dielectric layer having a thickness of between about 0.4 microns to about 0.8 microns.

19. The gate structure of claim 17, wherein the metal layer includes molybdenum having a thickness of between about 0.3 microns to about 0.6 microns, the metal layer comprising a gate terminal.

20. The gate structure of claim 17, wherein end portions of the side walls of the metal layer are disposed below the side walls of the dielectric layer disjoint sidewall regions a distance of between about 0.2 microns to about 2.0 microns.

21. The gate structure of claim 17, further comprising:

a drift region surrounding the dielectric layer second sides and the P+ Junction gate, the drift region being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC); and

a drain terminal adjacent to the drift region on a side opposite the P+ Junction gate, the drain terminal comprising a second metal layer consisting of a metal selected from the group consisting of aluminum (Al) and nickel (Ni).

22. The gate structure of claim 17, further comprising a source terminal adjacent to the dielectric layer on a side facing the metal layer interior region, the source terminal comprising a second metal layer consisting of a metal selected from the group consisting of aluminum (Al) and nickel (Ni).

23. A method of using a junction field effect transistor (JFET) transistor,

the JFET transistor comprising:

a dielectric layer deposited on side walls of a trench having side walls and a floor, each side wall having a first side facing into a trench interior region and a second side facing away from the trench interior region;

a metal layer formed into a U-shape deposited on the dielectric layer first sides and the floor of the of the trench surrounding a metal layer interior region, an end portion of the side walls of the metal layer being disposed below the side walls of the dielectric layer disjoint sidewall regions a distance of between about 0.5 microns to about 2.0 microns, the metal layer being electrically connected to a gate terminal;

an undoped poly-silicon layer deposited to fill the metal layer interior region, the undoped poly-silicon layer being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC);

a P+ Junction gate adjacent to a floor portion of the metal layer;

a drift region surrounding the dielectric layer second sides and the P+ Junction gate, the drift region being composed of a semiconductor material selected from the group consisting of silicon (Si) and silicon carbide (SiC);

a drain terminal adjacent to the drift region on a side opposite the P+ Junction gate;

a source terminal adjacent to the drift region on a side facing the metal layer interior region,

the method of using the JFET transistor comprising the operation of;

applying a controlling voltage to the gate terminal, the controlling voltage applied to the gate terminal being effective in controlling the flow of electrical current between the source terminal and the drain terminal.

24. The method of claim 23, wherein the dielectric layer is composed of a dielectric material selected from the group consisting of silicon-dioxide (SiO₂) and silicon-nitride (Si₃N₄), the dielectric layer having a thickness of between about 0.4 microns to about 0.8 microns.

25. The method of claim 23, wherein the metal layer includes molybdenum having a thickness of between about 0.3 microns to about 0.6 microns.