System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage

• US 20080086588A1
• Filed: 12/15/2006
• Published: 04/10/2008
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Danilak, Radoslav, Rajan, Suresh, Smith, Michael J.S.
• Granted Patent: US 8,055,833 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

Claims

1. An interface circuit configured to couple to one or more flash memory devices and further configured to couple to a host system, wherein the interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

2. The interface circuit as recited in claim 1 wherein the virtual flash memory device comprises a capacity greater than any one of the one or more flash memory devices.

4. The interface circuit as recited in claim 1 wherein the interface circuit is configured to compute one or more parameters of the virtual flash memory device.

5. The interface circuit as recited in claim 4 wherein the one or more parameters are reported to the host system during discovery of the flash memory configuration by the host system.

6. The interface circuit as recited in claim 1 wherein the interface circuit is configured to translate a protocol implemented by the host system to a protocol implemented by the one or more flash memory devices.

7. The interface circuit as recited in claim 1 wherein, if a block of data locations in the virtual flash memory device are detected to be bad, the interface circuit is configured to remap addresses in the block from a one set of storage locations in the one or more flash memory devices to a different set of storage locations in the one or more flash memory devices.

8. The interface circuit as recited in claim 1, wherein the interface circuit is configured to generate an erasure operation independent of a write operation.

9. The interface circuit as recited in claim 8 wherein the erasure operation erases a block in the one of the one or more flash memory devices, wherein the block has been marked as garbage for garbage collection.

10. The interface circuit as recited in claim 8 wherein the erasure operation is generated by the interface circuit to pre-erase unused blocks in the one or more flash memory devices.

11. The interface circuit as recited in claim 1 comprising one or more buffers configured to store write operations provided by the host system, wherein the interface circuit is configured to report that an erasure operation corresponding to a write operation has completed prior to actual completion of the erasure operation, and wherein the interface circuit is configured to store the write operation in the buffer until the erasure operation is actually complete.

3. The interface circuit as recited in claim 3 wherein the virtual flash memory device comprises a capacity equal to a sum of the capacities of the one or more flash memory devices.

12. An apparatus comprising:

one or more flash memory devices; and

an interface circuit coupled to the one or more flash memory devices and further configured to couple to a host system, wherein the interface circuit is configured to present a standard interface to the host system and is configured to provide another interface to the one or more flash memory devices that differs from the standard interface.

13. The apparatus as recited in claim 12 wherein the standard interface is pin-compatible with a previous generation of flash memory devices.

14. The apparatus as recited in claim 12 wherein the interface circuit and the one or more flash memory devices are stacked.

15. The apparatus as recited in claim 12 wherein the one or more flash memory devices and the interface circuit are integrated onto a single semiconductor substrate.

16. An apparatus comprising:

one or more flash memory devices;

a flash memory controller; and

an interface circuit coupled to the one or more flash devices and coupled to the flash memory controller, wherein the interface controller is configured to present at least one virtual flash memory device to the flash memory controller, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices.

17. The apparatus as recited in claim 16 wherein the interface circuit is configured to translate a protocol implemented by the flash memory controller to a protocol implemented by the one or more flash memory devices, and wherein the interface circuit may further be configured to translate the protocol implemented by the one or more flash memory devices to the protocol implemented by the flash memory controller.

18. The apparatus as recited in claim 16 wherein the protocol implemented by the flash memory controller is one of a NAND protocol or a NOR protocol and the protocol implemented by the flash memory controller is the other one of the NAND protocol and the NOR protocol.

19. A method comprising:

presenting at least one virtual flash memory device to a host system; and

implementing the virtual flash memory device using a combination of one or more flash memory devices.

20. The method as recited in claim 19 wherein the implementing comprises simulating one or more signals on the interface to the host system.

21. An interface circuit configured to couple to one or more flash memory devices and further configured to couple to a host system, wherein the interface circuit comprises translation circuitry configured to emulate at least at one attribute of a virtual flash memory device exposed to the host system using the one or more the flash memory devices.

22. The interface circuit as recited in claim 33 wherein the interface circuit includes logic configured to discover attributes of the one or more flash devices.