ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS

• US 20080086677A1
• Filed: 10/05/2007
• Published: 04/10/2008
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Yang, Xueshi, Wu, Zining
• Granted Patent: US 8,171,380 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block may be configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block may be configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells.

Claims

1. An apparatus, comprising:

a memory device including a plurality of memory cells;

a write block configured to write encoded data to the memory cells; and

an adaptive data encoding block configured to select a first coding scheme from a plurality of coding schemes to encode data to be written to a first group of one or more memory cells in the memory device, the selection of the first coding scheme being based at least in part on a first quality value of the first group of one or more memory cells.

2. The apparatus of claim 1, wherein the adaptive data encoding block is further configured to select a second coding scheme from the plurality of coding schemes to encode data to be written to a second group of one or more memory cells in the memory device, the selection of the second coding scheme being based at least in part on a second quality value of the second group of one or more memory cells.

3. The apparatus of claim 2, wherein the first and second coding schemes are different coding schemes.

4. The apparatus of claim 2, wherein if the first quality value of the first group of one or more memory cells is a higher quality value than the second quality value of the second group of one or more memory cells, then the first coding scheme is selected such that the first coding scheme has a lower error correction capability than the second coding scheme.

5. The apparatus of claim 4, further comprising a quality map to provide the quality values for the first group of one or more memory cells and the second group of one or more memory cells.

6. The apparatus of claim 1, further comprising a quality map to provide the first quality value for the first group of one or more memory cells.

7. The apparatus of claim 6, wherein said quality map is configured to store and provide a plurality of quality values for a plurality of groups of one or more memory cells in the memory device.

8. The apparatus of claim 7, wherein said quality map is configured to store and provide at least one quality value for at least one group of one or more memory cells in the memory device that indicates that the at least one group of one or more memory cells is or are to be excluded from being used.

9. The apparatus of claim 1, wherein the memory cells of the memory device are flash memory cells.

10. An apparatus, comprising:

a memory device including a plurality of memory cells;

a read block configured to read the memory cells; and

a data quality monitoring block configured to determine a first quality value of a first group of one or more memory cells included in the memory device, the determined first quality value being indicative of a quality of the first group of one or more memory cells and to be used at least in part for selecting a first coding scheme for writing data to the first group of one or more memory cells.

11. The apparatus of claim 10, wherein said data quality monitoring block is configured to determine the first quality value of the first group of one or more memory cells based, at least in part, on the reading of the first group of one or more memory cells by the read block.

12. The apparatus of claim 10, further comprising a quality map configured to include the first quality value of the first group of one or more memory cells determined by the data quality monitoring block.

13. The apparatus of claim 12, wherein said quality map is further configured to include, at any given moment in time, an additional quality value of the first group of one or more memory cells along with the first quality value of the first group of one or more memory cells, the additional quality value being stored in the quality map prior to storing the first quality value into the quality map.

14. The apparatus of claim 13, further comprising a signal processing and detection block to process data read by the read block from the first group of one or more memory cells, and an error correction and decoding block to decode data read by the read block from the first group of one or more memory cells.

15. The apparatus of claim 14, wherein said quality map is further configured to provide the additional quality value to the signal processing and detection block to facilitate said processing of the data.

16. The apparatus of claim 14, wherein said quality map is further configured to provide the additional quality value to the error correction and decoding block to facilitate said decoding of the data.

17. The apparatus of claim 10, wherein the data quality monitoring block is further configured to determine at least one quality value for at least one group of one or more memory cells in the memory device that indicates that the at least one group of one or more memory cells is or are to be excluded from being used.

18. The apparatus of claim 10, wherein the data quality monitoring block is further configured to determine a second quality value of a second group of one or more memory cells in the memory device based at least in part on the reading of the memory cells by the read block, the second quality value being indicative of the quality of the second group of one or more memory cells and to be used at least in part for selecting a coding scheme for writing data to the second group of one or more memory cells.

19. The apparatus of claim 18, further comprising a quality map configured to store the quality values of the first group of one or more memory cells and the second group of one or more memory cells determined by the data quality monitoring block.

20. The apparatus of claim 10, wherein the memory cells of the memory device are flash memory cells.

21. An apparatus, comprising:

a memory device including a plurality of memory cells; and

a quality map having stored therein a first quality value for a first group of one or more memory cells of the memory device, the first quality value to be used to facilitate selection of a first coding scheme from a plurality of coding schemes for encoding data to be written to the first group of one or more memory cells.

22. The apparatus of claim 21, wherein the quality map further having stored therein a second quality value for a second group of one or more memory cells of the memory device, the second quality value to be use to facilitate selection of a second coding scheme from the plurality of coding schemes for encoding data to be written to the second group of one or more memory cells.

23. The apparatus of claim 22, wherein if the first quality value is a higher quality value than the second quality value, then the first coding scheme is selected such that the first coding scheme has a lower error correction capability than the second coding scheme.

24. The apparatus of claim 21, wherein the memory device has multiple groups of one or more memory cells, and said quality map is configured to include for each group of one or more memory cells a corresponding quality value.

25. The apparatus of claim 24, wherein the quality map is further configured to additionally include, for each group of one or more memory cells and at any given moment in time, an additional corresponding quality value along with the corresponding quality value, the additional corresponding quality values of the groups of one or more memory cells being stored in the quality map prior to the storage of the corresponding quality values of the groups of one or more memory cells.

26. The apparatus of claim 21, wherein the quality map is configured to provide to a signal processing and detection block and/or an error correction and decoding block the first quality value to facilitate processing and/or decoding, respectively, of data stored in the first group of one or more memory cells

27. An apparatus, comprising:

a memory device including a plurality of memory cells;

a data quality monitoring block configured to determine a first quality value of a first group of one or more memory cells included in the memory device, the determined first quality value being indicative of a quality of the first group of one or more memory cells; and

an adaptive data encoding block configured to select a first coding scheme from a plurality of coding schemes to encode data to be written to the first group of one or more memory cells in the memory device, the selection of the first coding scheme being based at least in part on the determined first quality value of the first group of one or more memory cells.

28. The apparatus of claim 27, wherein the data quality monitoring block is further configured to determine a second quality value of a second group of one or more memory cells in the memory device, the second quality value being indicative of the quality of the second group of one or more memory cells.

29. The apparatus of claim 28, wherein the adaptive data encoding block is further configured to select a second coding scheme from the plurality of coding schemes to encode data to be written to the second group of one or more memory cells in the memory device, the selection of the second coding scheme being based at least in part on the second quality value of the second group of one or more memory cells.

30. The apparatus of claim 29, wherein if the first quality value is a higher quality value than the second quality value, then the first coding scheme is selected such that the first coding scheme has a lower error correction capability than the second coding scheme.

31. The apparatus of claim 27 further comprising a read block configured to read the memory cells, and wherein the data quality monitoring block is operatively coupled to the memory device via the read block.

32. The apparatus of claim 31, further comprising a quality map configured to include the first quality value of the first group of one or more memory cells determined by the data quality monitoring block.

33. The apparatus of claim 32, wherein said quality map is further configured to include, at any given moment in time, an additional quality value of the first group of one or more memory cells along with the first quality value of the first group of one or more memory cells, the additional quality value being stored in the quality map prior to storing the first quality value into the quality map.

34. The apparatus of claim 33, further comprising a signal processing and detection block configured to process data read by the read block from the first group of one or more memory cells, and an error correction and decoding block configured to decode data read by the read block from the first group of one or more memory cells.

35. The apparatus of claim 34, wherein said quality map is further configured to provide the additional quality value to the signal processing and detection block to facilitate said processing of the data.

36. The apparatus of claim 34, wherein said quality map is further configured to provide the additional quality value to the error correction and decoding block to facilitate said decoding of the data.

37. The apparatus of claim 27, further comprising a quality map configured to store and to provide the first quality value for the first group of one or more memory cells.

38. The apparatus of claim 37, wherein said quality map is further configured to store and to provide a plurality of quality values for a plurality of groups of one or more memory cells in the memory device.

39. The apparatus of claim 38, wherein said quality map is further configured to store and to provide at least one quality value for at least one group of one or more memory cells in the memory device that indicates that the at least one group of one or more memory cells is, or are, to be excluded from being used.

40. A method, comprising:

determining a first quality value of a first group of one or more memory cells included in a memory device, the determined first quality value being indicative of a quality of the first group of one or more memory cells; and

selecting a first coding scheme from a plurality of coding schemes to encode data to be written to the first group of one or more memory cells, the selection of the first coding scheme being based at least in part on the determined first quality value of the first group of one or more memory cells.

41. The method of claim 40, further comprising determining a second quality value of a second group of one or more memory cells in the memory device, the second quality value being indicative of the quality of the second group of one or more memory cells;

and

selecting a second coding scheme from the plurality of coding schemes to encode data to be written to the second group of one or more memory cells, the selection of the second coding scheme being based at least in part on the second quality value of the second group of one or more memory cells.

42. The method of claim 41, wherein if the first quality value is a higher quality value than the second quality value, then the first coding scheme is selected such that the first coding scheme has a lower error correction capability than the second coding scheme.

43. The method of claim 40, further comprising storing said first quality value in a quality map.

44. The method of claim 43, further comprising providing the stored first quality value in the quality map to a signal processing and detection block to facilitate processing of data read from the first group of one or more memory cells.

45. The method of claim 43, further comprising providing the stored first quality value in the quality map to an error correction and decoding block to facilitate decoding data read from the first group of one or more memory cells

46. The method of claim 40, further comprising determining at least one quality value for at least one group of one or more memory cells in the memory device that indicates that the at least one group of one or more memory cells is, or are, to be excluded from being used.

47. An apparatus, comprising:

means for determining a first quality value of a first group of one or more memory cells included in a memory device, the determined first quality value being indicative of a quality of the first group of one or more memory cells; and

means for selecting a first coding scheme from a plurality of coding schemes to encode data to be written to the first group of one or more memory cells, the selection of the first coding scheme being based at least in part on the determined quality value of the first group of one or more memory cells.

48. The apparatus of claim 47, further comprising means for determining a second quality value of a second group of one or more memory cells in the memory device, the second quality value being indicative of the quality of the second group of one or more memory cells;

and

means for selecting a second coding scheme from the plurality of coding schemes to encode data to be written to the second group of one or more memory cells, the selection of the second coding scheme being based at least in part on the second quality value of the secondgroup of one or more memory cells.

49. The apparatus of claim 48, wherein if the first quality value is a higher quality value than the second quality value, then the first coding scheme is selected such that the first coding scheme has a lower error correction capability than the second coding scheme.

50. The apparatus of claim 47, further comprising means for storing said first quality value.

51. The apparatus of claim 50, further comprising means for signal processing and detection, and said means for storing being configured to provide the stored first quality value to the means for signal processing and detection in order to facilitate processing of data read from the first group of one or more memory cells.

52. The apparatus of claim 50, further comprising means for error correction and decoding, and said means for storing being configured to provide the stored first quality value to the means for error correction and decoding to facilitate decoding of data read from the first group of one or more memory cells

53. The apparatus of claim 47, further comprising means for determining at least one quality value for at least one group of one or more memory cells in the memory device that indicates that the at least one group of one or more memory cells is, or are, to be excluded from being used.