Semiconductor device and manufacturing method thereof

• US 20080087923A1
• Filed: 01/11/2007
• Published: 04/17/2008
• Est. Priority Date: 10/12/2006
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Naoyoshi
• Granted Patent: US 7,968,920 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Claims

1. A semiconductor device having a MOS field-effect transistor, comprising:

a stress film formed to cover a source, a drain, a sidewall insulating layer and a gate,

wherein a slit extending from a surface of the stress film toward the sidewall insulating layer is formed in the stress film.

2. The semiconductor device according to claim 1, wherein the sidewall insulating layer is made of a plurality of insulating films each having a different constituent element.

3. The semiconductor device according to claim 1, wherein the slit is formed to extend to a source side end and drain side end of the sidewall insulating layer.

4. The semiconductor device according to claim 1, wherein the sidewall insulating layer is formed in an L shape.

5. The semiconductor device according to claim 4, wherein the slit is formed to extend near a bend section of the L-shaped sidewall insulating layer.

6. The semiconductor device according to claim 1, wherein the stress film for imparting a compressive strain to a channel is formed on the source, drain and gate of a p-channel MOS field-effect transistor.

7. The semiconductor device according to claim 1, wherein the stress film for imparting a tensile strain to a channel is formed on the source, drain and gate of an n-channel MOS field-effect transistor.

8. A method for manufacturing a semiconductor device having a MOS field-effect transistor, comprising the steps of:

forming a stress film to cover a source, a drain, a sidewall insulating layer and a gate; and

forming in the stress film a slit extending from a surface of the stress film toward the sidewall insulating layer.

9. The manufacturing method according to claim 8, wherein in the step of forming the slit, a wet treatment using hydrofluoric acid is performed.

10. The manufacturing method according to claim 8, wherein the slit is formed by forming the stress film such that an aspect ratio of the stress film for covering the gate is 3 or more.

11. The manufacturing method according to claim 8, wherein the slit is formed in the stress film by forming the gate to have an aspect ratio of 3 or more.

12. The manufacturing method according to claim 8, wherein in the step of forming the stress film, the stress film for imparting a compressive strain to a channel is formed on the source, drain and gate of a p-channel MOS field-effect transistor.

13. The manufacturing method according to claim 8, wherein in the step of forming the stress film, the stress film for imparting a tensile strain to a channel is formed on the source, drain and gate of an n-channel MOS field-effect transistor.