SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20080087949A1
• Filed: 09/12/2007
• Published: 04/17/2008
• Est. Priority Date: 10/17/2006
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation), Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: MARUOKA, Michiaki, TAKAYA, Hidefumi, HAMADA, Kimimori
• Application Number:
  US11/854,183
• Publication Number:
  US 20080087949A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity type;

a semiconductor layer of a second conductivity type on the substrate;

a buried region formed on a boundary between the substrate and the semiconductor layer;

a trench that passes through the semiconductor layer and the buried region and that reaches to the substrate;

a gate insulation film on an inside of the trench; and

a gate electrode surrounded by the gate insulation film in the trench;

the gate electrode having a portion faced with the semiconductor layer through the gate insulation film and a portion faced with the buried region through the gate insulation film.

2. A semiconductor device as claimed in claim 1, wherein the gate electrode is extended to a depth reaching to the substrate.

3. A semiconductor device as claimed in claim 1, wherein the semiconductor layer and the buried region form a super-junction structure.

4. A semiconductor device as claimed in claim 1, wherein the gate insulation film has a side wall portion on a side wall of the trench and a bottom portion on a bottom of the trench, the bottom portion being thicker than the side wall portion.

5. A semiconductor device as claimed in claim 1, wherein the first and the second conductivity types are an n-type and a p-type, respectively.

6. A semiconductor device as claimed in claim 1, wherein the first and the second conductivity types are a p-type and an n-type, respectively.

7. A semiconductor device as claimed in claim 1, wherein the semiconductor layer is formed by an epitaxial layer while the buried region is formed by ion implantation.

8. A semiconductor device as claimed in claim 1, wherein the semiconductor layer has an impurity concentration substantially equal to that of the buried region.

9. A semiconductor device comprising a plurality of vertical MOSFET'"'"'s, each of which comprises:

a substrate of a first conductivity type;

a semiconductor layer of a second conductivity type on the substrate;

a buried region formed on a boundary between the substrate and the semiconductor layer;

a trench that passes through the semiconductor layer and the buried region and that reaches to the substrate;

a gate insulation film on an inside surface of the trench; and

a gate electrode surrounded by the gate insulation film in the trench;

the gate electrode having a portion faced with the semiconductor layer through the gate insulation film and a portion faced with the buried region through the gate insulation film.

10. A semiconductor device as claimed in claim 9, wherein the plurality of the vertical MOSFET'"'"'s are formed in a region which includes the trenches arranged at a predetermined distance spaced between adjacent ones of the trenches.

11. A semiconductor device as claimed in claim 10, wherein each of the buried regions has a profile within the semiconductor layer, the profile including a portion substantially equal to a quarter of the predetermined distance.

12. A method of manufacturing a semiconductor device, comprising the steps of:

forming, on a substrate of a first conductivity type, a semiconductor layer of a second conductivity type different from the first conductivity type;

forming a buried region of the first conductivity type at a boundary between the substrate and the semiconductor layer;

forming a trench passing through the semiconductor layer and the buried region to reach the substrate;

forming an insulating film on an inner side of the trench; and

forming a gate electrode in the trench so as to be surrounded by the insulating film, the gate electrode having a portion partially facing the buried region.

13. A method as claimed in claim 12, wherein the step of forming the insulating film in the trench comprises the steps of:

forming a bottom insulating film at a bottom of the trench and

forming a side-wall insulating film on a side wall of the trench, the side-wall insulating film being thinner than the bottom insulating film.

14. A method as claimed in claim 12, wherein the step of forming the buried region is a step of forming the buried region by ion implantation.