Insulated Gate Semiconductor Device and Method for Producing the Same

• US 20080087951A1
• Filed: 09/28/2005
• Published: 04/17/2008
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Takaya, Hidefumi, Hamada, Kimimori, Miyagi, Kyosuke, Kuroyanagi, Akira, Tokura, Norihiko, Okura, Yasushi
• Granted Patent: US 8,076,718 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

Claims

1. An insulation gate type semiconductor device including a body region which is positioned on the upper surface inside a semiconductor substrate and is a first conductive type semiconductor;

and a drift region which is in contact with the downward of the body region and is a second conductive type semiconductor;

comprising;

a first trench portion group passing through the body region in the thickness direction of the semiconductor substrate, positioned in a cell area, and internally incorporating a gate electrode;

first floating regions enclosed by the drift region and surrounding the bottom portion of at least one trench portion in the first trench portion group, which is the first conductive type semiconductor;

a second trench portion group passing through the body region in the thickness direction of the semiconductor substrate, positioned in the terminal area surrounding the cell area, and formed to be annular so as to surround the cell area when being viewed from above; and

second floating regions enclosed by the drift region and surrounding the bottom portion of at least one trench portion in the second trench portion group, which is the first conductive type semiconductor;

wherein the semiconductor device is adapted such that electric field strength peak at two places in the semiconductor substrate in a thickness direction;

at a PN unction between the first or second floating regions and the drift region; and

at a PN junction between the body region and the drift region; and

wherein a gate electrode is internally incorporated in at least the innermost positioned trench portion in the second trench portion group; and

wherein a lower end of the gate electrode in the second trench portion group is equal to a lower end of the gate electrode in the first trench group in a position in the substrate in the thickness direction.

2. The insulation gate type semiconductor device according to claim 1, wherein at least the outermost positioned trench portion in the second trench portion group includes a gate-free structure.

3. The insulation gate type semiconductor device according to claim 1, wherein a gate electrode is internally incorporated in only the innermost positioned trench portion in the second trench portion group.

4. The insulation gate type semiconductor device according to claim 1, wherein the pitches of respective trench portions in the second trench portion group are narrower than those of respective trench portions in the first trench portion group.

5. The insulation gate type semiconductor device according to claim 1, wherein the inner trench portion of adjacent trench portions in the second trench portion group is deeper than the other.

6. The insulation gate type semiconductor device according to claim 1, wherein trench portions of the second trench portion group are deeper than trench portions of the first trench portion group.

7. The insulation gate type semiconductor device according to claim 6, wherein the width of trench portions of the second trench portion group is wider than the width of trench portions of the first trench portion group.

8. The insulation gate type semiconductor device according to claim 1, wherein the body region extends laterally to the outermost trench portion in the second trench portion group at a maximum.

9. A method for producing an insulation gate type semiconductor device including a body region which is positioned on the upper surface inside a semiconductor substrate and is a first conductive type semiconductor;

and a drift region which is in contact with the downward of the body region and is a second conductive type semiconductor;

a floating region which is surrounded by the drift region and is a first conductive type semiconductor; and

a structure wherein electric field strength peak at two places in the semiconductor substrate in the thickness direction;

at a PN junction between the floating region and the drift floating region; and

at a PN junction between the body region and the drift region, comprising the steps of;

forming a mask pattern to form the first trench portion group positioned in the cell area and the second trench portion group, which is positioned in the terminal area surrounding the cell area and surrounds the first trench portion group;

forming trench portions to compose respective trench portions by etching on the basis of the mask pattern formed in the mask pattern forming step;

forming an oxide film on a wall surface of a trench portion formed in the trench portions forming step;

after forming the oxide film in the oxide film forming step, implanting impurities to form floating regions, which is the first conductive type semiconductor, by implanting impurities from the bottom parts of respective trench portions formed in the trench portion forming step;

forming a deposition insulation layer by depositing an insulation substance in respective trench portions formed in the trench portion forming step;

etching back to form an etching protection layer in which the upper part of at least the innermost positioned trench portion in the second trench portion group is open, and to remove a part of the deposition insulation layer formed in the deposition insulation layer forming step; and

forming a gate electrode in a space produced in respective trench portions in the etching-back step.

10. The method for producing an insulation gate type semiconductor device according to claim 9, further including a step of forming a protective layer on a part of the semiconductor substrate before the mask pattern forming step, wherein the etching rate of the protective layer is greater than the etching rate of the mask layer during the trench forming step.

11. The method for producing an insulation gate type semiconductor device according to claim 9, wherein, in the trench portion forming step, the pattern width of the mask pattern to form trench portions in the second trench portion group is made wider than the pattern width of the mask pattern to form trench portions in the first trench portion group.

12. The method for producing an insulation gate type semiconductor device according to claim 9, including the step of carrying out thermal oxidation process after the etching back step and before the gate electrode forming step, and then carrying out wet etching.