STACKED IMAGER PACKAGE

• US 20080088014A1
• Filed: 09/26/2006
• Published: 04/17/2008
• Est. Priority Date: 09/26/2006
• Status: Active Grant

• Current Assignee: Smartsens Technology (Cayman) Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Rassel, Richard J., Sprogis, Edmund J., Leidy, Robert K., Jaffe, Mark D., Adkisson, James W., Luce, Stephen E.
• Granted Patent: US 7,361,989 B1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Claims

1-4. -4. (canceled)

14. A method of interconnecting chips in a chip package, comprising:

forming backside metallurgy on a first chip;

connecting said backside metallurgy on said first chip to pads on the active surface of said first chip by conductors extending from said backside metallurgy to said pads; and

connecting metallurgy on the active surface of a second chip to said backside metallurgy by an array of interchip solder bumps.

15. The method as set forth in claim 14 wherein said pads on said active surface of said first chip are positioned around the peripheral region of said active surface.

16. The method as set forth in claim 15 wherein said active surface of said first chip includes thereon an array of light sensitive pixels located within said pad positions around said peripheral region of said active surface of said first chip.

17. The method as set forth in claim 16 wherein said conductors are around-the-edge conductors extending conformally around the edge of said first chip to said pads.

18. The method as set forth in claim 16 wherein said conductors are through via conductors extending through said first chip to said pads.

19. The method as set forth in claim 16 wherein said first chip in an imaging chip and said second chip is a logic chip and wherein said imaging chip is mounted across an aperture in the wall of a carrier package so as to expose said light sensitive pixels.

20. The method as set forth in claim 19 wherein said imaging chip and said logic chip are electrically connected to said carrier package by wire bonding.

21. A chip package, comprising:

a first chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by through via conductors extending through said first chip from said backside metallurgy to said pads; and

a second chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said first chip by an array of interchip solder bumps.

22. A chip package, comprising:

an imaging chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by conductors extending from said backside metallurgy to said pads; and

a logic chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said imaging chip by an array of interchip solder bumps.

5. The chip package as set forth in claim 22 wherein the said active surface of said imaging chip includes thereon an array of light sensitive pixels located within the position of said pads around said peripheral region with said pixels arranged to generate voltage as a function of light.

6. The chip package as set forth in claim 5 wherein the said imaging chip is mounted across an aperture in the wall of a carrier package so as to expose said array of light sensitive pixels to light through said aperture.

7. The chip package as set forth in claim 6 wherein said imaging chip and said logic chip are electrically connected to said carrier package by wire bonding.

8. The chip package as set forth in claim 7 wherein said conductors are around-the-edge conductors extending conformally around the edge of said imaging chip to said pads.

9. The chip package as set forth in claim 7 wherein said conductors are through via conductors extending through said imaging chip to said pads.

10. The chip package as set forth in claim 5 wherein the backside of said logic chip is mounted on a carrier package.

11. The chip package as set forth in claim 10 wherein said logic chip is electrically connected to said carrier package by wire bonded at one end to pads on said logic chip and the other end to pads on said carrier package.

12. The chip package as set forth in claim 10 wherein said logic chip is electrically connected to said carrier package by an array of solder bumps with some of said solder bumps of said array of solder bumps connected by through vias to selected ones of said interchip solder bumps.

13. The chip package as set forth in claim 5 wherein the planar area of said logic chip is smaller than the planar area of said imaging chip.