Structure and manufacturing method of a chip scale package
First Claim
Patent Images
1. A chip package comprising:
- a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;
a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer, wherein said passivation layer comprises polymer, and wherein said first pad comprises copper;
a copper pillar between said first pad and said first surface, wherein said copper pillar has a height between 10 and 100 micrometers;
a barrier metal layer between said first pad and said copper pillar, wherein said barrier metal layer is on said first pad, over said passivation layer and in said opening, wherein said barrier metal layer comprises titanium;
a solder metal between said copper pillar and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;
an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and
a contact ball on said second surface.
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Abstract
A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
109 Citations
20 Claims
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1. A chip package comprising:
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a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;
a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer, wherein said passivation layer comprises polymer, and wherein said first pad comprises copper;
a copper pillar between said first pad and said first surface, wherein said copper pillar has a height between 10 and 100 micrometers;
a barrier metal layer between said first pad and said copper pillar, wherein said barrier metal layer is on said first pad, over said passivation layer and in said opening, wherein said barrier metal layer comprises titanium;
a solder metal between said copper pillar and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;
an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and
a contact ball on said second surface. - View Dependent Claims (2, 3, 4, 5)
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6. A chip package comprising:
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a substrate;
a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer, wherein said passivation layer comprises polymer, and wherein said first pad comprises copper;
a copper pillar between said first pad and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers;
a barrier metal layer between said first pad and said copper pillar, wherein said barrier metal layer is on said first pad, over said passivation layer and in said opening, wherein said barrier metal layer comprises titanium;
a solder metal between said copper pillar and said substrate, wherein said solder metal is joined with said substrate; and
an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal. - View Dependent Claims (7, 8, 9, 10)
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11. A chip package comprising:
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a ball grid array (BGA) substrate having a first surface and a second surface opposite to said first surface;
a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer, wherein said first pad comprises copper;
a copper pillar between said semiconductor device and said first surface, wherein said copper pillar is connected to said first pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers;
a solder metal between said copper pillar and said first surface, wherein said solder metal is joined with said ball grid array (BGA) substrate;
an underfill between said semiconductor device and said first surface, wherein said underfill contacts with said semiconductor device and said first surface and encloses said copper pillar and said solder metal; and
a contact ball on said second surface. - View Dependent Claims (12, 13, 14, 15)
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16. A chip package comprising:
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a substrate;
a semiconductor device comprising a passivation layer and a first pad exposed by an opening in said passivation layer, wherein said first pad comprises copper;
a copper pillar between said semiconductor device and said substrate, wherein said copper pillar is connected to said first pad through said opening, and wherein said copper pillar has a height between 10 and 100 micrometers;
a solder metal between said copper pillar and said substrate, wherein said solder metal is joined with said substrate; and
an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar and said solder metal. - View Dependent Claims (17, 18, 19, 20)
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Specification