DOUBLE DATA RATE SERIAL ENCODER

• US 20080088492A1
• Filed: 11/09/2007
• Published: 04/17/2008
• Est. Priority Date: 11/23/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Steele, Brian, Musfeldt, Curtis, Wiley, George
• Granted Patent: US 8,730,069 B2
• Time in Patent Office: Days
• US Class Current: 341/98
• CPC Class Codes: H03M 7/16 Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code

Abstract

A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Claims

1. A method for serial encoding, comprising:

providing a glitch-less multiplexer (mux) having a plurality of mux data inputs, a plurality of select inputs and a mux output, wherein the mux output does not glitch due to a change of any single select input bit;

providing a plurality of latches, having latch data inputs and latch data outputs, wherein the latch data outputs are coupled to the plurality of mux data inputs;

providing an enabler, coupled to the latches;

providing a counter, coupled to the select inputs of the mux, wherein the counter transitions on either a rising or a falling edge of an input clock, and only a single counter state bit changes on a transition between any two consecutive states in a count sequence;

employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing; and

employing the counter to select one of the plurality of mux data inputs in a predetermined sequence for the mux output and control the enabler.

2. The method of claim 1 further comprising employing the counter to provide the mux with input selection values according to a Gray code sequence.

3. The method of claim 2 further comprising employing an output selection algorithm included in the mux and optimized based on a priori knowledge of the Gray code sequence to provide a glitch-less output only during input transitions in accordance with the Gray code sequence, thereby reducing the size of the mux.

4. The method of claim 3 wherein employing an output selection algorithm included in the mux and optimized based on a priori knowledge of the Gray code sequence to provide a glitch-less output only during input transitions in accordance with the Gray code sequence includes employing the output selection algorithm to select the mux output in accordance with the following:

5. The method of claim 3 further comprising:

transitioning the counter at every edge of the input clock; and

outputting from the mux a bit at every edge of the input clock.

6. The method of claim 2 wherein employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing includes employing the enabler to enable the latches based on the input selection values generated by the counter.

7. The method of claim 1 wherein employing the enabler to enable and control the latches to update the latch data outputs at a time when the latch data inputs are not changing includes employing the enabler to update only a subset of the latches while selecting another subset of the latches for output by the mux.

8. The method of claim 1 further comprising:

receiving data as input in parallel; and

outputting the data onto a serial communications link.

9. A method for serial encoding, comprising:

storing a plurality of input bits;

generating an input selection sequence by employing a counter that transitions on either a rising or a falling edge of an input clock, and for which a single counter state bit to change on a transition between any two consecutive states in a count sequence; and

outputting serially said plurality of input bits according to said input selection sequence, wherein outputting serially includes outputting serially without glitches during input transitions in said input selection sequence.

10. The method of claim 9 further comprising updating the plurality of stored input bits.

11. The method of claim 9 wherein generating an input selection sequence includes generating a Gray code sequence.

12. The method of claim 11 wherein outputting serially includes outputting serially based on an output selection algorithm optimized based on a priori knowledge of the Gray code sequence.

13. The method of claim 12 wherein outputting serially said plurality of input bits according to said input selection sequence includes outputting serially without glitch only during input transitions in accordance with the Gray code sequence.

14. The method of claim 9 wherein outputting serially said plurality of input bits according to said input selection sequence includes outputting a bit at every edge of the input clock.