DISPLAY DEVICE

• US 20080088568A1
• Filed: 10/12/2007
• Published: 04/17/2008
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Beihai HKC Optoelectronics Technology Company Limited
• Original Assignee: NEC LCD Technologies Limited (Tianma Microelectronics Company Limited)
• Inventors: Haga, Hiroshi, Asada, Hideki, Kaneko, Setsuo
• Granted Patent: US 8,773,344 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 3/18 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

Disclosed is a display device for use of a surface display of an arbitrary shape, including a plural number of display element units, each made up of a circuit that forms a single stage of a scanning circuit and a pixel circuit connected to an output of the scanning circuit, are arranged in a unicursal fashion on a display substrate.

Claims

1. A surface display device comprising:

a plurality of display element units arranged with one stroke on a display substrate;

each of said display element units including;

a unit circuit constituting a single stage of a scanning circuit; and

a pixel circuit connected to an output node of said unit circuit.

2. The surface display device according to claim 1, wherein said scanning circuit is driven by a single-phase clock signal.

3. The surface display device according to claim 1, wherein said unit circuit constituting a single stage of said scanning circuit includes a transistor that outputs a scanning signal to an output node;

wherein

said transistor outputting the scanning signal to the output node and the single pixel circuit are arranged as a set to constitute said display element unit and a plurality of said sets of said transistors and the pixel circuits are arrayed together to form substantially the entire area of a display area.

4. The surface display device according to claim 3, wherein transistors in said scanning circuit and transistors in said pixel circuits include polysilicon TFTs formed on a glass substrate to constitute an active matrix liquid crystal display device.

5. The surface display device according to claim 1, wherein said scanning circuit is arranged on the display substrate with one or more folded parts to render it possible to form a non-rectangular display area.

6. The surface display device according to claim 1 wherein said scanning area is arranged spirally on said display substrate to form a non-rectangular display area.

7. The surface display device according to claim 1, wherein a part of said scanning circuit is arranged between neighboring ones of said pixel circuits or underneath said pixel circuit.

8. The surface display device according to claim 1, wherein a circuit including said pixel circuits and said scanning circuit is arranged on the display substrate so as to have at least one bend.

9. The surface display device according to claim 1, wherein a spirally extending array of said pixel circuits and said scanning circuit is arranged on the display substrate.

10. The surface display device according to claim 1, wherein a flexible linear display unit including said pixel circuits and said scanning circuit that are linearly arranged is wrapped at least two turns on a support.

11. The surface display device according to claim 1, wherein said unit circuit constituting a single stage of said scanning circuit includes a circuit that receives a scanning signal from a previous stage to output said scanning signal to an output node of said unit circuit responsive to a clock signal;

said pixel circuit including a display element and a pixel switch that on/off controls the connection between a data signal and the display element responsive to the scanning signal from the unit circuit associated therewith.

12. An electronic device including the surface display device as set forth in claim 1.

13. An ornamental product including the surface display device as set forth in claim 1.

14. A display device comprising:

a plurality of pixel circuits each including a display element and a pixel switch that on/off controls the connection between a data signal and the display element responsive to a scanning signal applied thereto; and

a scanning circuit that sequentially applies the scanning signal to the pixel circuits;

said pixel switch including a transistor having a gate electrode connected to an associated one of output nodes of the scanning circuit;

wherein

output nodes of odd stage unit circuits of said scanning circuit, each output a scanning signal of a first polarity;

output nodes of even stage unit circuits of said scanning circuit each output a scanning signal of a second polarity opposite to said first polarity;

the transistors constituting the pixel switches connected to said output nodes of odd stage unit circuits of said scanning circuit are each of a first conductivity type; and

the transistors constituting the pixel switches connected to said output nodes of even stage unit circuits of said scanning circuit are each of a second conductivity type.

15. The display device according to claim 14, wherein the odd stage unit circuits of said scanning circuit each include:

an inverter circuit that receives a pulse signal supplied from a previous stage; and

a switching transistor of a second conductivity type connected between an output node of said inverter circuit and an output node of said unit circuit;

wherein

the even stage unit circuits of said scanning circuit each include;

an inverter circuit that receives a pulse signal supplied from a previous stage; and

a switching transistor of a first conductivity type connected between an output node of said inverter circuit and the output node of said unit circuit; and

wherein

a common clock signal is applied to the gate electrodes of said switching transistors of said unit circuits of said odd and even stages of said scanning circuit.

16. The display device according to claim 14, wherein the odd stage unit circuits and the even stage unit circuits of said scanning circuit each include

a clocked inverter that receives a pulse signal supplied from a previous stage;

an output node of said clocked inverter being an output node of the unit circuit;

wherein

a clock signal is supplied to the gate electrode of the transistor of the second conductivity type of the clocked inverter in the odd stage unit circuit of said scanning circuit; and

a signal obtained by inverting said clock signal is supplied to the gate electrode of the transistor of the first conductivity type of said clocked inverter; and

wherein

a signal obtained by inverting said clock signal is supplied to the gate electrode of the transistor of the second conductivity type of said clocked inverter in the even stage unit circuit of said scanning circuit; and

said clock signal is supplied to the gate electrode of the transistor of the first conductivity type of said clocked inverter.

17. The display device according to claim 14, wherein the odd stage unit circuits and the even stage unit circuits of said scanning circuit each include:

an inverter circuit that receives a pulse signal from a previous stage; and

a CMOS transmission gate connected between an output node of said inverter circuit and an output node of said unit circuit;

wherein

a clock signal is supplied to the gate electrode of the transistor of the second conductivity type of said CMOS transmission gate in the odd stage unit circuit of said scanning circuit; and

a signal obtained by inverting said clock signal is supplied to the gate electrode of the transistor of the first conductivity type of said CMOS transmission gate; and

wherein

a signal obtained by inverting said clock signal is supplied to the gate electrode of said transistor of the second conductivity type of the CMOS transmission gate in the even stage unit circuit of said scanning circuit; and

said clock signal is supplied to the gate electrode of said transistor of the first conductivity type of the CMOS transmission gate.

18. The display device according to claim 14, wherein the even stage unit circuits and the odd stage unit circuits of said scanning circuit each include

a single-phase clock controlled inverter comprising:

first to fourth switch devices, sequentially connected in series between a high potential side power supply and a low potential side power supply;

wherein

said first and second switch devices are each a p-type MOS transistor; and

said third and fourth switch devices are each an n-type MOS transistor;

gate electrodes of one of said p-type MOS transistors and one of said n-type MOS transistors being connected in common and receiving a pulse signal supplied from a previous stage;

while a clock signal is supplied to the gates of the remaining two MOS transistors;

drain electrodes of said one of said p-type MOS transistors and said one of said n-type MOS transistors being connected in common to constitute the output node of the unit circuit.

19. A display device comprising:

a plurality of stages of unit circuits stringed together to form a scanning circuit;

said unit circuits each receiving a scanning signal from an input terminal or from a previous stage and outputting said scanning signal from an output node thereof responsive to an input clock signal; and

a plurality of pixel circuits arranged in association with said unit circuits of said scanning circuit;

wherein

said pixel circuit includes a pixel switch that is on/off controlled responsive to the scanning signal output from said associated unit circuit of said scanning circuit, and a display element unit in which a data signal is written when said pixel switch is on; and

wherein

a display area of said display device may be configured to any one of linear, planar and stereoscopic shapes.