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Configurable ports for a host ethernet adapter

  • US 20080089358A1
  • Filed: 12/10/2007
  • Published: 04/17/2008
  • Est. Priority Date: 04/01/2005
  • Status: Active Grant
First Claim
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1. An Ethernet adapter comprising:

  • a plurality of layers for receiving and transmitting packets from and to a processor;

    wherein the plurality of layers include a common high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes can be configured in different modes of operation, wherein each of the different modes of operation comprise data repetition at a bit level, each bit being repeated N times, N being the frequency multiplication ratio being used for a particular mode of operation of the high speed serdes.

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