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Microelectronic packages fabricated at the wafer level and methods therefor

  • US 20080090333A1
  • Filed: 10/17/2006
  • Published: 04/17/2008
  • Est. Priority Date: 10/17/2006
  • Status: Active Grant
First Claim
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1. A method of making microelectronic packages comprising:

  • making a subassembly includingproviding a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces,attaching a compliant layer to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate,providing electrically conductive features on said compliant layer;

    after making said subassembly, juxtaposing said plate with a semiconductor wafer having a top surface and contacts accessible at the top surface;

    attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer;

    electrically interconnecting at least some of the electrically conductive features on said compliant layer and the contacts on said semiconductor wafer.

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