Microelectronic packages fabricated at the wafer level and methods therefor

• US 20080090333A1
• Filed: 10/17/2006
• Published: 04/17/2008
• Est. Priority Date: 10/17/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Humpston, Giles
• Granted Patent: US 7,759,166 B2
• Time in Patent Office: Days
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29034 the layer connector covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/484 : Connecting portions
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer.

Claims

1. A method of making microelectronic packages comprising:

making a subassembly including

providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces,

attaching a compliant layer to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate,

providing electrically conductive features on said compliant layer;

after making said subassembly, juxtaposing said plate with a semiconductor wafer having a top surface and contacts accessible at the top surface;

attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer;

electrically interconnecting at least some of the electrically conductive features on said compliant layer and the contacts on said semiconductor wafer.

2. The method as claimed in claim 1, wherein the attaching said compliant layer to said plate step comprises using an adhesive to attach said compliant layer and said plate together.

3. The method as claimed in claim 1, wherein the attaching said plate to said semiconductor wafer step comprises using an adhesive to attach said plate and said semiconductor wafer together.

4. The method as claimed in claim 1, wherein said plate is made of a dielectric material.

5. The method as claimed in claim 1, wherein said plate is rigid.

6. The method as claimed in claim 1, wherein said plate and said semiconductor wafer having matching coefficients of thermal expansion.

7. The method as claimed in claim 1, wherein said plate comprises a material selected from the group consisting of glass and silicon.

8. The method as claimed in claim 1, wherein the openings in said plate have larger diameters at the top surface of said plate and smaller diameters at the bottom surface of said plate.

9. The method as claimed in claim 8, wherein the openings in said plate have side walls.

10. The method as claimed in claim 9, wherein the side walls are tapered between the top and bottom surfaces of said plate.

11. The method as claimed in claim 10, wherein said electrically conductive features on said compliant layer extend into the openings in said plate.

12. The method as claimed in claim 9, wherein each of the side walls includes a ledge.

13. The method as claimed in claim 12, wherein said electrically conductive features extend onto said ledges.

14. The method as claimed in claim 1, wherein said electrically conductive features are selected from the group consisting of conductive traces, conductive bond ribbons, conductive terminals, conductive bond pads and conductive posts.

15. The method as claimed in claim 1, wherein the electrically interconnecting step comprises forming a wire bond connection between the contacts on said wafer and said electrically conductive features on said compliant layer.

16. The method as claimed in claim 15, further comprising encapsulating said wire bond with an encapsulant material.

17. The method as claimed in claim 1, further comprising providing a solder mask or a dielectric film over at least one of said electrically conductive features on said compliant layer.

18. A method of making microelectronic packages comprising:

making a subassembly including

providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, said plate including ledges extending into each said opening so that each said opening has a larger diameter adjacent the top surface of said plate and a smaller diameter adjacent the bottom surface of said plate,

attaching a compliant layer to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate,

providing electrically conductive features on said compliant layer, wherein at least some of said electrically conductive features extend onto said ledges;

after making said subassembly, providing a semiconductor wafer having a top surface and contacts accessible at the top surface;

attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer;

electrically interconnecting the contacts on said semiconductor wafer with said electrically conductive features.

19. The method as claimed in claim 18, wherein the attaching said compliant layer to said plate step comprises using an adhesive to attach said compliant layer and said plate together.

20. The method as claimed in claim 18, wherein the attaching said plate to said semiconductor comprises using an adhesive to attach said plate and said semiconductor wafer together.

21. The method as claimed in claim 18, wherein said plate and said semiconductor wafer having matching coefficients of thermal expansion.

22. The method as claimed in claim 18, wherein at least some of said electrically conductive features are selected from the group consisting of conductive traces, conductive bond ribbons, conductive terminals, conductive bond pads and conductive posts.

23. The method as claimed in claim 18, wherein at least some of said electrically conductive features are accessible at the top surface of said compliant layer.

24. The method as claimed in claim 18, wherein the electrically interconnecting step comprises forming wire bonds between the contacts on said wafer and the at least some of said electrically conductive features extending onto said ledges.

25. The method as claimed in claim 24, further comprising encapsulating said wire bond with an encapsulant material.

26. The method as claimed in claim 18, wherein said compliant layers comprises a plurality of compliant bumps that are spaced from one another.

27. The method as claimed in claim 18, further comprising, after the electrically interconnecting step, dicing said semiconductor wafer to provide a plurality of microelectronic packages.

28. The method as claimed in claim 18, further comprising plating conductive posts atop said conductive features so that said conductive posts project from the top surface of said compliant layer.

29. A method of making microelectronic packages comprising:

making a subassembly including

providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces,

attaching a flexible dielectric substrate to the top surface of said plate, said flexible dielectric substrate having openings extending therethrough that are aligned with the openings extending through said plate,

providing electrically conductive features on said flexible dielectric substrate;

after making said subassembly, providing a semiconductor wafer having a top surface and contacts accessible at the top surface;

attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer;

electrically interconnecting at least some of the electrically conductive features on said flexible dielectric substrate and the contacts on said semiconductor wafer.

30. A method of making a microelectronic assembly comprising:

making a subassembly including

providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces,

attaching a compliant layer to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate,

providing electrically conductive features on said compliant layer;

after making said subassembly, juxtaposing the bottom surface of said plate with a semiconductor wafer having a top surface and contacts accessible at the top surface;

attaching the bottom surface of said plate with the top surface of said semiconductor wafer so that the openings extending through said plate and said compliant layer are aligned with the contacts on said semiconductor wafer;

electrically interconnecting at least some of said electrically conductive features on said compliant layer and the contacts on said semiconductor wafer.

31. The method as claimed in claim 30, wherein the attaching a compliant layer step comprises disposing an adhesive layer between said compliant layer and the top surface of said plate for attaching said compliant layer to said plate.

32. The method as claimed in claim 31, wherein the attaching the bottom surface of said plate step comprises applying a second adhesive layer to the bottom surface of said plate and abutting said second adhesive layer against the top surface of said semiconductor wafer.

33. The method as claimed in claim 30, wherein the electrically interconnecting step comprises using wire bonds for electrically interconnecting the contacts on said semiconductor wafer with the at least some of said electrically conductive features on said compliant layer.

34. The method as claimed in claim 30, wherein said plate has a thickness that is non-uniform.

35. The method as claimed in claim 30, wherein said plate has a reduced thickness adjacent at least one of the openings extending through said plate.

36. The method as claimed in claim 30, wherein said plate includes a shelf adjacent at least one of the openings extending through said plate, said shelf defining a wire bonding land that is located between the top surface of said plate and the bottom surface of said plate.

37. The method as claimed in claim 36, wherein the electrically conductive features on said compliant layer include conductive traces, at least one of said conductive traces extending to the wire bonding land provided on the shelf of said plate.

38. The method as claimed in claim 36, wherein the electrically interconnecting step comprises attaching a first end of a wire bond to one of the contacts on said semiconductor wafer and a second end of the wire bond to the wire bonding land provided on the shelf of said plate.

39. The method as claimed in claim 30, wherein said plate and said semiconductor wafer have coefficients of thermal expansion that are substantially similar.

40. A microelectronic packages comprising:

a subassembly including

a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, said plate including ledges extending into each said opening so that each said opening has a larger diameter adjacent the top surface of said plate and a smaller diameter adjacent the bottom surface of said plate,

a compliant layer attached to the top surface of said plate, said compliant layer having openings that are aligned with the openings extending through said plate,

electrically conductive features provided on said compliant layer, wherein at least some of said electrically conductive features extend onto said ledges;

a semiconductor wafer having a top surface and contacts accessible at the top surface, wherein the bottom surface of said plate is attached with the top surface of said semiconductor wafer so that the openings extending through said plate are aligned with the contacts on said wafer, and wherein the contacts on said semiconductor wafer are electrically interconnected with said electrically conductive features.