Method for Forming Inter-Poly Dielectric in Shielded Gate Field Effect Transistor
First Claim
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1. A method of forming a field effect transistor, comprising:
- forming a trench in a silicon region of a first conductivity type;
forming a shield electrode in a lower portion of the trench;
forming an inter-poly dielectric (IPD) comprising a layer of thermal oxide and a layer of conformal dielectric along an upper surface of the shield electrode; and
forming a gate electrode in the trench over the IPD.
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Abstract
A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.
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Citations
31 Claims
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1. A method of forming a field effect transistor, comprising:
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forming a trench in a silicon region of a first conductivity type;
forming a shield electrode in a lower portion of the trench;
forming an inter-poly dielectric (IPD) comprising a layer of thermal oxide and a layer of conformal dielectric along an upper surface of the shield electrode; and
forming a gate electrode in the trench over the IPD. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming a field effect transistor (FET), the method comprising:
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forming a trench extending into a silicon region of a first conductivity type;
forming a shield electrode in a lower portion of the trench; and
forming an inter-poly dielectric (IPD) having a concave profile along at least a center portion of its upper surface over the shield electrode; and
forming a gate electrode in the trench over the IPD. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of forming a field effect transistor (FET), the method comprising:
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forming a trench extending into a silicon region of a first conductivity type;
forming a shield electrode in a lower portion of the trench; and
forming an inter-poly dielectric (IPD) having a convex profile along its lower surface and a concave profile along its upper surface over the shield electrode; and
forming a gate electrode in the trench over the IPD. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification