Shallow source MOSFET

• US 20080090357A1
• Filed: 11/09/2007
• Published: 04/17/2008
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Ho, Moses, Tai, Sung-Shan, Li, Tiesheng, Chang, Hong
• Granted Patent: US 8,008,151 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a hard mask on a substrate having a top substrate surface;

forming a trench in the substrate, through the hard mask;

depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface; and

removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

2. A method of fabricating a semiconductor device as recited in claim 1, wherein the hard mask is a SiO₂ hard mask.

3. A method of fabricating a semiconductor device as recited in claim 1, wherein the trench is formed to be mutually aligned with the hard mask.

4. A method of fabricating a semiconductor device as recited in claim 1, further comprising implanting a body in the substrate, implanting a source, patterning a layer of dielectric material on the surface of the device, and forming an ohmic contact region in the body via an opening left by the dielectric material pattern.

5. A method of fabricating a semiconductor device as recited in claim 1, further comprising implanting a body in the substrate, implanting a source, patterning a layer of dielectric material on the surface of the device, etching an opening through the source, and implanting an ohmic contact region.

6. A method of fabricating a semiconductor device as recited in claim 1, further comprising forming a source.

7. A method of fabricating a semiconductor device as recited in claim 1, further comprising forming a contact.

8. A method of fabricating a semiconductor device as recited in claim 7, wherein the contact formation is self-aligned.