Performance or power-optimized code/data storage for nonvolatile memories

• US 20080090604A1
• Filed: 10/17/2006
• Published: 04/17/2008
• Est. Priority Date: 10/17/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Dover, Lance W.
• Granted Patent: US 7,644,225 B2
• Time in Patent Office: Days
• US Class Current: 455/550.1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement

Abstract

A wireless device incorporates a nonvolatile memory that dynamically controls a swapping or mapping of bit pairs for a selected memory region to optimize programming times.

Claims

1. A wireless device, comprising:

a processor; and

a nonvolatile memory having a memory bit swap encoder to characterize code received from the processor to find a dominant level for the code to be stored in a region of the nonvolatile memory where the swap encoder substitutes a swapped level with the dominant level before storage to reduce programming time.

2. The wireless device of claim 1 further including the swap encoder substitutes the swapped level with the dominant level before storage to reduce programming current.

3. The wireless device of claim 1 wherein the region of the nonvolatile memory further includes at least two additional memory bits to retain information about the swapped level.

4. The wireless device of claim 3 wherein the memory bit swap encoder further maps each threshold voltage range of the characterized code to optimize programming times in storing the code in the region of the nonvolatile memory.

5. The wireless device of claim 4 where a program operation stores the code in the region of the nonvolatile memory using the substituted swapped level for the dominant level and a read operation restores the code using the at least two additional memory bits.

6. A wireless device comprising:

multiple antennas to receive an over-the-air signal;

a transceiver to receive a modulated signal from the multiple antennas;

a processor coupled to the transceiver; and

a bit swap encoder to characterize programming code executed by the processor to determine a dominant level for a set memory region, where the bit swap encoder substitutes a level having a programming time that is less than a programming time associated with the dominant level to program the set memory region.

7. The wireless device of claim 6 wherein the level having a programming time that is less than a programming time associated with the dominant level is an erase level.

8. The wireless device of claim 6 wherein the dominant level is one of four threshold voltage ranges.

9. The wireless device of claim 6 wherein the level is an erase level having a programming time that is less than a programming time associated with the dominant level.

10. A wireless device comprising a nonvolatile memory having a memory bit swap encoder to characterize code before storage in a memory region to determine a dominant level and swapping the dominant level with a swapped level selected to reduce programming time.

11. The wireless device of claim 10 wherein the swapped level is an erase level having a programming time that is less than a programming time associated with the dominant level.

12. The wireless device of claim 11 wherein the memory region of the nonvolatile memory further includes at least two additional memory bits to retain mapping information about the swapped level and the dominant level.

13. The wireless device of claim 12 wherein the at least two additional memory bits are used to restore the code in a read operation of the memory region.

14. A method of using a nonvolatile memory comprising:

characterizing threshold voltage Vt encodings for a data pattern associated with a memory region;

choosing a dominant threshold voltage for the memory region;

mapping an erase threshold voltage as a substitute for the dominant threshold voltage; and

programming the data pattern in the nonvolatile memory using the erase threshold voltage substituted for the dominant threshold voltage.

15. The method of claim 14 further including storing information in the memory region that indicates mapping the erase threshold voltage as the substitute for the dominant threshold voltage.

16. The method of claim 15 further including mapping each threshold voltage to minimize programming times.

17. The method of claim 16 further including reading the data pattern stored in the memory region using the information that indicates mapping each threshold voltage.

18. A wireless device comprising:

a processor; and

a nonvolatile memory having a memory bit swap encoder to characterize code received from the processor to determine a prominent level associated with programming the code in a region of the nonvolatile memory, wherein the memory bit swap encoder substitutes a swapped level having a programming time that is less than a programming time associated with the prominent level.

19. The wireless device of claim 18 further including storing information in the memory region that describes a mapping of the main level with the swapped level.

20. The wireless device of claim 18 wherein the memory bit swap encoder substitutes the swapped level with the dominant level to reduce programming current.