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Shared interrupt controller for a multi-threaded processor

  • US 20080091867A1
  • Filed: 12/12/2007
  • Published: 04/17/2008
  • Est. Priority Date: 10/18/2005
  • Status: Active Grant
First Claim
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1. A multi-threaded processor comprising:

  • a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor, the sequencer including an interrupt controller to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt of the one or more interrupts;

    wherein the interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt after the at least one interrupt is selected for service by the first thread.

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