Shared interrupt controller for a multi-threaded processor

• US 20080091867A1
• Filed: 12/12/2007
• Published: 04/17/2008
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, William, Codrescu, Lucian, Plondke, Erich, Ahmed, Muhammad, Venkumahanti, Suresh
• Granted Patent: US 7,984,281 B2
• Time in Patent Office: Days
• US Class Current: 710/261
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.

Claims

1. A multi-threaded processor comprising:

a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor, the sequencer including an interrupt controller to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt of the one or more interrupts;

wherein the interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt after the at least one interrupt is selected for service by the first thread.

2. The processor of claim 1, wherein the interrupt controller includes a plurality of operating modes.

3. The processor of claim 2, wherein a first operating mode of the plurality of operating modes comprises an interrupt active high mode responsive to a logic high interrupt.

4. The processor of claim 2, wherein a second operating mode of the plurality of operating modes comprises an interrupt active low mode responsive to a logic low interrupt.

5. The processor of claim 2, wherein a third operating mode of the plurality of operating modes comprises an edge triggered operating mode responsive to a rising or falling edge of signal.

6. The processor of claim 2, wherein a fourth operating mode of the plurality of operating modes comprises a level triggered operating mode responsive to a level portion of a signal.

7. The processor of claim 1, wherein the interrupt controller is adapted to set a flag in an interrupt pending register, the flag corresponding to at least one of the one or more interrupts.

8. The processor of claim 7, wherein the flag is set while the at least one interrupt is being serviced by the first thread.

9. The processor of claim 1, further comprising a global interrupt register accessible to each thread of the one or more threads to take an interrupt, the interrupt controller to alter the global interrupt register to prevent access to the interrupt by the second thread while the first thread services the at least one interrupt.

10. The processor of claim 1, further comprising an interrupt pending register associated with each of the one or more threads, the interrupt pending register accessible to the interrupt controller, the interrupt controller to control a bit of the interrupt pending register to indicate when the first thread is servicing the at least one interrupt.

11. The processor of claim 10, wherein the bit is cleared from the interrupt pending register automatically after the interrupt serviced by the thread is de-asserted.

12. A processor comprising:

a global interrupt register responsive to one or more interrupt sources to receive one or more interrupts, the global interrupt register accessible by each thread of a plurality of threads of a multi-threaded processor to service the one or more interrupts; and

interrupt logic coupled to the global interrupt register, the interrupt logic to determine that an interrupt of the one or more interrupts is being serviced by a thread of the multi-threaded processor and to selectively prevent access to the interrupt by any other thread of the plurality of threads.

13. The processor of claim 12, further comprising an interrupt automatic disable register including a plurality of bits corresponding to bits of the global interrupt register, the interrupt automatic disable register accessible by the interrupt logic to set a selected bit of the plurality of bits, the selected bit associated with the interrupt, wherein the selected bit indicates that an interrupt is being serviced and wherein the logic prevents the other threads from accessing the interrupt while the interrupt is being serviced.

14. The processor of claim 13, wherein the interrupt logic is adapted to receive an instruction to clear the selected bit after the interrupt is de-asserted and wherein the interrupt logic clears the selected bit in response to receiving the instruction.

15. The processor of claim 12, further comprising an interrupt pending register that includes a plurality of bits, each bit of the plurality of bits indicating a status of a particular interrupt, wherein the interrupt logic has access to the interrupt pending register to set a selected bit corresponding to the interrupt.

16. The processor of claim 15, wherein the interrupt comprises a software interrupt and wherein the interrupt pending register is accessible to software to provide a status indicator for the software interrupt.

17. A method of controlling interrupts in a multi-threaded processor, the method comprising:

receiving an interrupt at a sequencer associated with a multi-threaded processor, the sequencer including a global interrupt register accessible to a plurality of threads of the multi-threaded processor and including an interrupt control circuit; and

preventing access to the interrupt by a second thread of the plurality of threads after determining the interrupt is being serviced by a first thread of the plurality of threads.

18. The method of claim 17, further comprising setting a bit related to the received interrupt at the global interrupt register.

19. The method of claim 17, further comprising setting a bit associated with the first thread in an interrupt pending register to indicate that the interrupt is being serviced.

20. The method of claim 17, further comprising:

receiving a clear flag instruction related to an interrupt flag that is set in the global interrupt register; and

clearing a corresponding flag of an automatic disable register, wherein processing logic prevents access to the interrupt based on a state of the corresponding flag.

21. The method of claim 17, wherein preventing access to the interrupt comprises setting a bit in an interrupt automatic disable register that relates to a corresponding bit of the global interrupt register, wherein processing logic prevents access to the interrupt when the corresponding bit of the global interrupt register is set.

22. A processing device comprising:

means for receiving an interrupt at a sequencer associated with a multi-threaded processor having a plurality of threads, the sequencer including a global interrupt register accessible to the plurality of threads and including an interrupt control circuit; and

means for preventing access to the interrupt by a second thread of the plurality of threads after determining the interrupt is being serviced by a first thread of the plurality of threads.

23. The device of claim 22 further comprising:

means for receiving an indication that that the interrupt has been serviced; and

means for clearing a bit in an interrupt automatic disable register corresponding to the interrupt in response to receiving the indication.

24. The device of claim 22 further comprising means for setting a bit related to the interrupt received at the global interrupt register.

25. A wireless communications device comprising:

a transceiver to communicate with a communications network;

a memory including a plurality of instructions executable by a processor; and

the processor coupled to the transceiver and having access to the memory, the processor comprising;

a plurality of threads adapted to execute selected instructions from the plurality of instructions; and

a sequencer adapted to retrieve and provide the selected instructions to the plurality of threads, the sequencer including a global interrupt register accessible to each execution unit of the plurality of threads and including an interrupt controller coupled to the global interrupt register, the interrupt controller adapted to determine when a thread of the plurality of threads is servicing an interrupt and to utilize the global interrupt register to prevent access to the interrupt by other threads of the plurality of threads.

26. The device of claim 25, wherein the global interrupt register includes an interrupt automatic disable (IAD) register, the IAD register including a plurality of bits related to a corresponding plurality of interrupts.

27. The device of claim 25, wherein the interrupt controller is adapted to set a bit of the plurality of bits within the IAD register.

28. A processor comprising:

a first configuration register indicating an interrupt logic level;

a second configuration register indicating an interrupt trigger;

an automatic disable interrupt register including a plurality of bits, each bit of the plurality of bits corresponding to a particular interrupt; and

processing logic to provide an interrupt to a first thread of a multi-threaded processor including a plurality of execution threads based on the interrupt logic level, the interrupt trigger, and the bit corresponding to the particular interrupt, the processing logic to set the bit corresponding to the particular interrupt when the particular interrupt is being serviced by the first thread and to prevent access by other threads of the plurality of execution threads while the particular interrupt is being serviced by the first thread.

29. The processor of claim 28, wherein the processing logic further comprises a first multiplexer including an interrupt input responsive to an interrupt source, an output, and an interrupt logic level select input responsive to the first configuration register to selectively provide an incoming interrupt to the output.

30. The processor of claim 29, wherein the processing logic further comprises:

an edge detection circuit coupled to the output and adapted to detect a rising or falling edge of the incoming interrupt; and

a level detection circuit couple to the output and adapted to detect a logic level of the incoming interrupt.

31. The processor of claim 28, wherein the processing logic further comprises a second multiplexer including a second interrupt input, a second output, and an interrupt trigger selection input responsive to the second configuration register to selectively provide data related to the incoming interrupt to the second output.