Method and apparatus for queuing memory access commands in a memory queue of an information handling system
First Claim
1. A method of accessing information in a memory, the method comprising:
- providing an address queue including a plurality of queue entry locations, each queue entry location including a main information location and a supplemental information location;
testing, by a queue controller, first and second memory access commands to determine if the first and second memory access commands refer to consecutive memory locations in a memory;
storing the first memory access command and a portion of the second memory access command in the same queue entry location of the memory queue if the testing step determines that the first and second memory access commands refer to consecutive memory locations in the memory; and
storing the first memory access command and the second memory access command in different queue entry locations, respectively, of the memory queue if the testing step determines that first and second memory access commands do not refer to consecutive memory locations in the memory.
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Accused Products
Abstract
A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.
38 Citations
20 Claims
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1. A method of accessing information in a memory, the method comprising:
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providing an address queue including a plurality of queue entry locations, each queue entry location including a main information location and a supplemental information location; testing, by a queue controller, first and second memory access commands to determine if the first and second memory access commands refer to consecutive memory locations in a memory; storing the first memory access command and a portion of the second memory access command in the same queue entry location of the memory queue if the testing step determines that the first and second memory access commands refer to consecutive memory locations in the memory; and storing the first memory access command and the second memory access command in different queue entry locations, respectively, of the memory queue if the testing step determines that first and second memory access commands do not refer to consecutive memory locations in the memory. - View Dependent Claims (2, 3, 4, 5)
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6. A method of accessing information in a memory, the method comprising:
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providing an address queue including a plurality of queue entry locations, each queue entry location including a main information location and a supplemental information location; receiving, by a queue controller, a plurality of memory access commands including a new memory access command that refers to a target address; storing, by the queue controller, a subset of the target address of the new memory access command in the supplemental information location of a particular queue entry location if the subset corresponds to the target address of another memory access command stored in the main information location of the particular queue entry location; and otherwise storing, by the queue controller, the full target address of the new memory access command in a main information location of a queue entry location other than the particular queue entry location. - View Dependent Claims (7, 8, 9, 10)
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11. A memory controller, comprising:
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a queue controller that receives a plurality of memory access commands including a new memory access command that refers to a target address; an address queue, coupled to the queue controller, including a plurality of queue entry locations, each queue entry location including a main information location and a supplemental information location; wherein the queue controller stores a subset of the target address of the new memory access command in the supplemental information location of a particular queue entry location if the subset corresponds to the target address of another memory access command stored in the main information location of the particular queue entry location, and wherein otherwise the queue controller stores the full target address of the new memory access command in a main information location of a queue entry location other than the particular queue entry location. - View Dependent Claims (12, 13, 14, 15)
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16. An information handling system (IHS) comprising:
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a processor; a memory; and a memory controller coupled to the processor and the memory to control memory operations of the memory, the memory controller including; a queue controller that receives a plurality of memory access commands including a new memory access command that refers to a target address; an address queue, coupled to the queue controller, including a plurality of queue entry locations, each queue entry location including a main information location and a supplemental information location; wherein the queue controller stores a subset of the target address of the new memory access command in the supplemental information location of a particular queue entry location if the subset corresponds to the target address of another memory access command stored in the main information location of the particular queue entry location, and wherein otherwise the queue controller stores the full target address of the new memory access command in a main information location of a queue entry location other than the particular queue entry location. - View Dependent Claims (17, 18, 19, 20)
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Specification