MEMORY CONTROL APPARATUS

• US 20080091889A1
• Filed: 07/24/2007
• Published: 04/17/2008
• Est. Priority Date: 10/06/2006
• Status: Abandoned Application

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Hayano, Masahiko
• Application Number:
  US11/781,999
• Publication Number:
  US 20080091889A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Problem: A master cannot use a built-in memory as an independent memory in the case where a memory does not use peripherals.

Solution: A memory control apparatus includes main memories (for example, RAM) 35-1, 35-2, peripherals 40-1, 40-2 having built-in memories (for example, RAM) 43-1, 43-2, a master 20 for accessing the main memoirs and the built-in memories, and a access mode setting register for setting the access mode of the access object. Furthermore, the memory control apparatus includes an address decoder 31 for decoding an address from the master 20 and outputting the decoding results, and selectors 42-1, 42-2 for selecting access information including the decoding results being given to the built-in memories corresponding to the set access mode.

Claims

1. A memory control apparatus being characterized by comprising;

a peripheral being configured to include a built-in memory storing data;

a master being configured to output an address to said main memory and said built-in memory and access said main memory and said built-in memory;

a mode setting device being configured to set an access mode of the access object to said main memory and said built-in memory;

a decoding device being configured to decode said address from said master according to said set access mode and output decoding results thereof; and

a selector being configured to select an access information including said decoding results given to said built-in memory corresponding to said set access mode;

2. The memory control apparatus according to claim 1 being characterized by further comprising;

an address setting device being configured to set start addresses of said main memory and said built-in memory, and provide said address decoding device with said set start addresses so that said address decoding device decodes said set start address comparing said set start address with said address from said master.

3. The memory control apparatus according to claim 1, wherein said master, said main memory, and said peripheral are connected to each other through a bus.

4. The memory control apparatus according to claim 1, wherein said main memory and said built-in memory are memories rewritable and readable at any time.

5. The memory control apparatus according to claim 1, wherein said mode setting device is a mode setting register.

6. The memory control apparatus according to claim 1, wherein said decoding device is a decoding circuit.

7. The memory control apparatus according to claim 1, wherein said address setting device is an address setting register.