Apparatus and method for directing micro architectural memory region accesses

• US 20080091917A1
• Filed: 10/11/2006
• Published: 04/17/2008
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Alexander, Bill, Held, James P., Rodgers, Scott D., Robinson, Scott H., Dixon, Martin G., Datta, Sham M., Smith, Larry O.
• Granted Patent: US 8,521,969 B2
• Time in Patent Office: Days
• US Class Current: 712/1
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2141 Access rights, e.g. capability lists, access control lists, access tables, access matrices

Abstract

In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

Claims

1. An apparatus comprising:

an integrated circuit having an input port to receive a memory access request and to be coupled with a system memory, wherein the system memory includes an at least one micro-architectural memory region that is to store one or more of instructions and data and is to be exclusively accessible by a micro-architectural agent, the integrated circuit including,

memory access director to direct the memory access request to the at least one micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and that the micro-architectural agent is operating in a micro-architectural memory region access mode.

2. The apparatus of claim 1, wherein the memory access director to direct the memory access request to an abort memory region located within the system memory if the memory access request includes a location within the micro-architectural memory region and detects at least one of that the micro-architectural agent did not originate the request and that the micro-architectural agent is not operating in the micro-architectural memory region access mode.

3. The apparatus of claim 2, wherein the integrated circuit further comprises:

a plurality of storage areas including a first and second storage area to store a first and second set of bits that define the at least one micro-architectural memory region;

region monitor coupled with the input port and the memory access director to determine whether the memory access request includes the location within the at least one micro-architectural memory region;

access mode detector coupled with the access mode director to detect whether the memory access request was originated by the micro-architectural agent operating in the micro-architectural memory region access mode.

4. The apparatus of claim 3, wherein the access mode detector to detect whether the memory access request was originated by the micro-architectural agent operating in the micro-architectural memory region access mode by one of reading a first one or more bits encoded within the memory access request, and reading a second one or more bits stored by the micro-architectural agent within the integrated circuit.

5. The apparatus of claim 4, wherein the integrated circuit is a processor including the at least one micro-architectural agent and wherein a set of information stored within the at least one micro-architectural memory region to be accessed by the processor to at least one of implement a micro-processor instruction and store micro-processor state information.

6. A method comprising:

removing a lock that prevents alteration of a set of values, the set of values including a first set of values that define a first micro-architectural memory region of a system memory located within a computer system;

disabling the first micro-architectural memory region from being accessible by one or more micro-architectural agent located within the computer system;

replacing the first set of values with a second set of values to establish a default memory region of the system memory; and

receiving a third set of values that define a second micro-architectural memory region, wherein the third set of values replace the second set of values to establish the second micro-architectural memory region.

7. The method of claim 6, wherein removing the lock, disabling the first micro-architectural memory region and replacing the first set of values are caused by one or more of executing a microcode and a computer system reset signal.

8. The method of claim 7, wherein the third set of values are received from a software code associated with the computer system, wherein the software code is stored external to the one or more micro-architectural agent.

9. The method of claim 6, wherein the second micro-architectural region is caused to be enabled when one or more conditions related to the second micro-architectural region is satisfied, and wherein the second micro-architectural region is accessible exclusively by the one or more micro-architectural agent when the second micro-architectural region is enabled.

10. The method of claim 9, further comprising:

erasing a first set of memory locations within the first micro-architectural memory region before the second micro-architectural memory region is caused to be enabled.

11. The method of claim 9, wherein satisfaction of the one or more conditions related to the second micro-architectural memory region is selected from the group consisting of one or more of:

detecting no overlap between the second micro-architectural memory region and an other memory region of the system memory, detecting that a plurality of micro-architectural agents within the computer system share the second micro-architectural memory region, and detecting that a set of communication paths to the second micro-architectural memory region are secure.

12. The method of claim 11, wherein the one or more micro-architectural agent includes one or more processor, and wherein the chipset is used as a common reference to detect whether the plurality of micro-architectural agents share the second micro-architectural memory region.

13. The method of claim 9 wherein the set of values is locked to prevent the first set of values from being changed without authorization.

14. A machine-readable medium containing instructions which, when executed by a processing system, cause the processing system to perform an operation, the operation comprising:

removing a lock that prevents a set of values from being changed, the set of values including a first set of values that define a first micro-architectural memory region of a system memory located within a computer system;

disabling the micro-architectural memory region from being accessible by one or more micro-architectural agent located within the computer system;

replacing the first set of values with a second set of values to establish a default memory region of the system memory; and

receiving a third set of values that define a second micro-architectural memory region, wherein the third set of values replace the second set of values to establish the second micro-architectural memory region.

15. The machine-readable medium of claim 14, wherein removing the lock, disabling the first micro-architectural memory region and replacing the first set of values are caused by one or more of executing a microcode and a computer system reset signal.

16. The machine-readable medium of claim 15, wherein the third set of values are received from a software code associated with the computer system, wherein the software code is stored external to the one or more micro-architectural agent.

17. The machine-readable medium of claim 14, wherein the second micro-architectural region is caused to be enabled when one or more conditions related to the second micro-architectural region is satisfied, and wherein the second micro-architectural region is accessible exclusively by the one or more micro-architectural agent when the second micro-architectural region is enabled.

18. The machine-readable medium of claim 17, further comprising:

erasing a first set of memory locations within the first micro-architectural memory region before the second micro-architectural memory region is caused to be enabled.

19. The machine-readable medium of claim 17, wherein satisfaction of the one or more conditions related to the second micro-architectural memory region is selected from the group consisting of one or more of:

detecting no overlap between the second micro-architectural memory region and an other memory region of the system memory, detecting that a plurality of micro-architectural agents within the computer system share the second micro-architectural memory region, and detecting that a set of communication paths to the second micro-architectural memory region are secure.

20. The machine-readable medium of claim 19, wherein the plurality of micro-architectural agents include one or more processor, wherein the chipset is used as a common reference to detect whether the plurality of micro-architectural agents share the second micro-architectural memory region.

21. The machine-readable medium of claim 17 wherein the set of values is locked to prevent the first set of values from being changed without authorization.

22. A system comprising:

a chipset coupled between an input output device, a graphics logic, an at least one processor and a system memory, wherein the system memory includes an at least one micro-architectural memory region that is to store one or more of instructions and data and to be exclusively accessible by a micro-architectural agent, the chipset and at least one processor including,

memory access director to direct the memory access request to the at least one micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

23. The apparatus of claim 22, wherein the memory access director to direct the memory access request to an abort region located within system memory if the memory access request includes a location within the micro-architectural memory region and the micro-architectural agent did not generate the request or the micro-architectural agent is not operating in the micro-architectural memory access mode.

24. The apparatus of claim 23, wherein the integrated circuit further comprises:

a plurality of storage areas including a first and second storage area to store a first and second set of bits that define the at least one micro-architectural memory region;

region monitor coupled with the input port and the memory access director to determine whether the memory access request includes the location within the at least one micro-architectural memory region;

access mode detector coupled with the access mode director to detect whether the memory access request originated at the micro-architectural agent operating in the micro-architectural memory region access mode.

25. The apparatus of claim 24, wherein the access mode detector to determine whether the memory access request was originated by the micro-architectural agent operating in the micro-architectural memory region access mode by one of reading a first one or more bits encoded within the memory access request, and reading a second one or more bits stored by the micro-architectural agent within the integrated circuit.

26. The system of claim 25, wherein the at least one processor includes a plurality of processors and each of the plurality of processors and the chipset share the one or more micro-architectural memory region within system memory.

27. The system of claim 26, wherein the at least one micro-architectural memory region includes a plurality of micro-architectural memory regions and the at least one processor includes a plurality of processors, and the chipset includes the first and second storage area to store the first and second set of bits that define each of the plurality memory regions, and wherein at least one of the plurality of processors does not share an entire one of the plurality of micro-architectural memory regions with an other of the plurality of processors.