Data stream prefetching in a microprocessor

• US 20080091922A1
• Filed: 12/10/2007
• Published: 04/17/2008
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Albert Williams, Bradly Frey, Cathy May, Edward Silha, Eric Fluhr, Francis O'Connell, Hung Le, John Griswell
• Original Assignee: Albert Williams, Bradly Frey, Cathy May, Edward Silha, Eric Fluhr, Francis O'Connell, Hung Le, John Griswell
• Inventors: Frey, Bradly, Griswell, John, Silha, Edward, Williams, Albert, O'Connell, Francis, May, Cathy, Le, Hung, Fluhr, Eric
• Granted Patent: US 7,904,661 B2
• Time in Patent Office: Days
• US Class Current: 712/207
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions

Abstract

A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Claims

1. A compiler comprising a set of computer executable instructions for generating object code from a source code file, the compiler being stored on a computer readable medium, comprising:

computer code means for identifying a data stream associated with a program, wherein the data stream comprises a sequence of memory addresses that reference two or more contiguous cache lines;

computer code means for determining a depth associated with the data stream based upon prefetch factors including the number of concurrent data streams and data consumption rates associated with the concurrent data streams; and

computer code means for enabling prefetch hardware in the processor to allocate data prefetch requests associated with the data stream to reflect the determined depth of the data stream.

2. The computer program product of claim 1, wherein the computer code means for allocating data prefetch requests includes computer code means for allocating prefetch requests for a number of cache lines adjacent and contiguous to a cache line currently being referenced by the program, wherein the number of cache lines is equal to the determined depth.

3. The computer program product of claim 1, further comprising, responsive to determining the depth associated with a data stream, computer code means for configuring prefetch hardware to reflect the determined depth for the identified data stream.

4. The computer program product of claim 3, wherein the computer code means for configuring the prefetch hardware comprises computer code means for setting prefetch control bits in an instruction inserted in the object code.

5. The computer program product of claim 4, wherein the prefetch control bits include a field of bits indicative of a depth associated with the data stream and an indicator of the number of bytes in the data stream.

6. The computer program product of claim 5, wherein a specified value in the field of bits indicative of the depth indicates the default depth for the data stream.

7. A processor, comprising:

at least one execution unit for processing load and store instructions;

prefetch hardware coupled to the at least one execution unit and configured to receive addresses generated by the execution unit;

wherein the prefetch hardware is configured to allocate prefetch requests responsive to receiving the generated addresses;

wherein the prefetch hardware includes configurable bits that control the depth of prefetch requests to be allocated responsive to receiving a generated address; and

wherein the configurable bits that control the depth of the prefetch requests to be allocated are configured according to prefetch factors including a number of concurrent data streams and data consumption rates associated with the concurrent data streams.

8. The processor of claim 7, wherein the prefetch hardware is configured to use a first depth to control the depth of prefetch requests associated with addresses associated with a first data stream and to use a different second depth to control the depth of prefetch requests associated with a second data stream.

9. The processor of claim 7, wherein the depth determines a number of cache lines to be prefetched, wherein the cache lines to be prefetched are adjacent and contiguous to a cache line currently being referenced by a program.

10. The processor of claim 7, wherein the configurable bits are controlled by a field of bits in an instruction executed by the processor.

11. The processor of claim 10, wherein the configurable bits are controlled by a field of prefetch control bits in a data cache block touch instruction.

12. The processor of claim 7, wherein the processor includes a default depth indicator and wherein a data stream has the default depth unless explicitly overridden by a value in the configurable bits.

13. The processor of claim 7, wherein the processor is configured to allocate L1 and L2 prefetch requests responsive to a load instruction but only L2 prefetch requests responsive to a store instruction.