Method and software for group floating-point arithmetic operations

• US 20080091925A1
• Filed: 07/27/2007
• Published: 04/17/2008
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Incorporated
• Inventors: Moussouris, John, Hansen, Craig, Massalin, Alexia
• Granted Patent: US 7,730,287 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple data elements, the instructions selected from an instruction set that includes group arithmethic instructions and group data handling instructions, (b) in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways, and (c) in response to decoding different group arithmethic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Claims

1. A method of processing data in a programmable processor, the method comprising:

decoding instructions for execution using an execution unit coupled to a register file comprising a plurality of registers, the execution unit operable to execute instructions by partitioning data stored in registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmethic instructions and group data handling instructions;

in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways and returning the re-arranged data to a register in the register file; and

in response to decoding different group arithmethic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the group arithmetic instructions include first, second, and third group multiply-and-add instructions each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements and partitions data in a third register in the register file into a third plurality of data elements which are equal in size to one another,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce a plurality of products,

(iii) adds each product in the plurality of products to a corresponding data element in the third register to produce the plurality of individual results, and

(iv) provides the plurality of individual results as the catenated result,

wherein the first group multiply-and-add instruction multiplies data elements of 8-bit integer data and adds data elements of 16-bit integer data, the second group multiply-and-add instruction multiplies data elements of 16-bit integer data and adds data elements of 32-bit integer data, and the third group multiply-and-add instruction multiplies data elements of 32-bit floating point data and adds data elements of 32-bit floating-point data.

2. The method of claim 1 wherein the catenated result is provided to a fourth register in the register file.

3. The method of claim 1 wherein the group arithmetic instructions further include first, second, and third group multiply instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another,

(iii) provides the plurality of individual results as the catenated result,

wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.

4. The method of claim 3 wherein the group arithmetic instructions further include first, second, third, and fourth group add instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and

(iii) provides the plurality of individual results as the catenated result,

wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data.

5. The method of claim 4 wherein the group arithmetic instructions further include a group negate instruction that partitions a first register in the register file into a first plurality of equal-sized data elements and applies a negation function to each data element in the first register to produce a plurality of negated data elements and provide the plurality of negated data elements as the catenated result, wherein the group negate instruction operates on data elements of 32-bit floating-point data.

6. The method of claim 5 wherein the group arithmetic instructions further include a group absolute value instruction that partitions a first register in the register file into a first plurality of equal-sized data elements and applies an absolute value function to each data element in the first register to produce a plurality of absolute-valued data elements and provide the plurality of absolute-valued data elements as the catenated result, wherein the group absolute instruction operates on data elements of 32-bit floating-point data.

7. The method of claim 6 wherein the instruction set further includes a scalar arithmetic add instruction that adds a first operand from a first register in the register file to a second operand from a second register in the register file to produce an addition result and provide the addition result to a register in the register file;

and wherein the execution unit is further capable of executing a scalar arithmetic subtract instruction that subtracts a first operand from a first register in the register file from a second operand from a second register in the register file to produce a subtraction result and provide the subtraction result to a register in the register file.

8. The method of claim 7 wherein the instruction set further includes a count instruction on an operand contained in a register in the register file to produce a count value indicative of a location of a transition in the operand from (a) consecutive bits following a most significant bit that are the same as the value of the most significant bit to (b) remaining bits in the operand and provide the count value to a register in the register file.

9. The method of claim 8 wherein the count value represents a number of remaining bits in the operand.

10. A method of processing data in a programmable processor, the method comprising:

decoding instructions for execution using an execution unit coupled to a register file comprising a plurality of registers, the execution unit operable to execute instructions by partitioning data stored in operand registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmethic instructions and group data handling instructions;

in response to decoding different group data handling instructions, executing group data handling operations that re-arrange data elements in different ways and returning the re-arranged data to a register in the register file; and

in response to decoding different group arithmethic instructions, executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the group arithmetic instructions include first, second, and third group multiply instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another,

(iii) provides the plurality of individual results as the catenated result,

wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.

11. The method of claim 10 wherein the group arithmetic instructions further include first, second, third, and fourth group add instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and

(iii) provides the plurality of individual results as the catenated result,

wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data.

12. A computer-readable storage medium:

having instructions stored thereon that instruct a computer system to perform operations using an execution unit coupled to a register file comprising a plurality of registers, by partitioning data stored in operand registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmethic instructions and group data handling instructions,

the instructions including different group data handling instructions that cause the execution unit to re-arrange data elements in different ways and returning the re-arranged data to a register in the register file,

the instructions further including different group arithmetic instructions for performing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the group arithmetic instructions include first, second, and third group multiply-and-add instructions each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements and partitions data in a third register in the register file into a third plurality of data elements which are equal in size to one another,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce a plurality of products,

(iii) adds each product in the plurality of products to a corresponding data element in the third register to produce the plurality of individual results, and

(iv) provides the plurality of individual results as the catenated result,

wherein the first group multiply-and-add instruction multiplies data elements of 8-bit integer data and adds data elements of 16-bit integer data, the second group multiply-and-add instruction multiplies data elements of 16-bit integer data and adds data elements of 32-bit integer data, and the third group multiply-and-add instruction multiplies data elements of 32-bit floating point data and adds data elements of 32-bit floating-point data.

13. The computer-readable storage medium of claim 12 wherein the catenated result is provided to a fourth register in the register file.

14. The computer-readable storage medium of claim 12 wherein the group arithmetic instructions further include first, second, and third group multiply instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another,

(iii) provides the third plurality of individual results as the catenated result,

wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.

15. The computer-readable storage medium of claim 14 wherein the group arithmetic instructions further include first, second, third, and fourth group add instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and

(iii) provides the plurality of individual results as the catenated result,

wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data.

16. The computer-readable storage medium 15 wherein the group arithmetic instructions further include a group negate instruction that partitions a first register in the register file into a first plurality of equal-sized data elements and applies a negation function to each data element in the first register to produce a plurality of negated data elements and provide the plurality of negated data elements as the catenated result, wherein the group negate instruction operates on data elements of 32-bit floating-point data.

17. The computer-readable storage medium of claim 16 wherein the group arithmetic instructions further include a group absolute value instruction that partitions a first register in the register file into a first plurality of equal-sized data elements and applies an absolute value function to each data element in the first register to produce a plurality of absolute-valued data elements and provide the plurality of absolute-valued data elements as the catenated result, wherein the group absolute instruction operates on data elements of 32-bit floating-point data.

18. The computer-readable storage medium of claim 17 wherein the instruction set further includes a scalar arithmetic add instruction that adds a first operand from a first register in the register file to a second operand from a second register in the register file to produce an addition result and provide the addition result to a register in the register file;

and wherein the execution unit is further capable of executing a scalar arithmetic subtract instruction that subtracts a first operand from a first register in the register file from a second operand from a second register in the register file to produce a subtraction result and provide the subtraction result to a register in the register file.

19. The computer-readable storage medium of claim 18 wherein the instruction set further includes a count instruction on an operand contained in a register in the register file to produce a count value indicative of a location of a transition in the operand from (a) consecutive bits following a most significant bit that are the same as the value of the most significant bit to (b) remaining bits in the operand and provide the count value to a register in the register file.

20. The computer-readable storage medium of claim 19 wherein the count value represents a number of remaining bits in the operand.

21. A computer-readable storage medium:

having instructions stored thereon that instruct a computer system to perform operations using an execution unit coupled to a register file comprising a plurality of registers, by partitioning data stored in operand registers in the register file into multiple data elements, the instructions selected from an instruction set that includes group arithmethic instructions and group data handling instructions,

the instructions including different group data handling instructions that cause the execution unit to re-arrange data elements in different ways returning the re-arranged data to a register in the register file,

the instructions further including different group arithmetic instructions for performing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the group arithmetic instructions include first, second, and third group multiply instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) multiplies each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another,

(iii) provides the plurality of individual results as the catenated result,

wherein the first group multiply instruction operates on data elements of 8-bit integer data and produces data elements of 16-bit integer data, the second group multiply instruction operates on data elements of 16-bit integer data and produces data elements of 32-bit integer data, and the third group multiply instruction operates on data elements of 32-bit floating-point data and produces data elements of 32-bit floating-point data.

22. The computer-readable storage medium of claim 21 wherein the group arithmetic instructions further include first, second, third, and fourth group add instructions, each of which

(i) partitions data in first and second registers in the register file into a first plurality and a second plurality of equal-sized data elements,

(ii) adds each data element in the first register with a corresponding data element in the second register to produce the plurality of individual results, which are equal in size to one another, and

(iii) provides the plurality of individual results as the catenated result,

wherein the first group add instruction operates on data elements of 8-bit integer data, the second group add instruction operates on data elements of 16-bit integer data, the third group add instruction operates on data elements of 32-bit integer data, and the fourth group add instruction operates on data elements of 32-bit floating-point data.