DISCRETE POWER CONTROL OF COMPONENTS WITHIN A COMPUTER SYSTEM

• US 20080091965A1
• Filed: 10/11/2007
• Published: 04/17/2008
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: GEFFROY, Laurent, ARORA, Sonu, NYCHKA, Robert J. P., VERMA, Vipin
• Granted Patent: US 9,146,600 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Claims

1. A system, comprising:

a subsystem comprising a plurality of components, each component configurable to operate at one or more of a plurality of power levels;

a control register coupled to the plurality of components and comprising a plurality of bits, each bit uniquely associated with a single component of the plurality of components; and

a power controller coupled to the plurality of components and configurable to cause the plurality of components to operate at the one or more of the plurality of power levels;

wherein the power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level of the plurality of power levels; and

wherein a first component of the plurality of components, associated with an asserted bit of the control register, operates at a second power level of the plurality of power levels corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

2. The system of claim 1, wherein a second component of the plurality of components, associated with a non-asserted bit within the control register, operates at the first power level in response to the transition signaled by the power controller.

3. The system of claim 1, wherein the subsystem is a memory subsystem.

4. The system of claim 1, wherein the plurality of power levels comprises a full-power level, a reduced-power level, and a powered-down level.

5. The system of claim 1, wherein the first component comprises a memory array within a memory device.

6. The system of claim 1, wherein the first component comprises periphery logic within a memory device.

7. The system of claim 1,

wherein the first component comprises a memory array, a third component comprises periphery logic, and a third power level is associated with the third component;

and

wherein the first, second and third power levels are each controlled independently by individual bits within the control register.

8. The system of claim 7, wherein the configuration of each of the first, second and third power levels determines a mode of operation comprising at least one mode selected from the group consisting of an Active mode, a Retention mode, a Sleep mode, a Retention-Till-Access mode, and an Active-On-Demand mode.

9. The system of claim 1, further comprising a processor, wherein software executing on the processor controls the state of the bits within the control register.

10. An integrated circuit (IC), comprising:

a processor core;

a memory subsystem coupled to the processor core and comprising a plurality of memories;

a control register coupled to the processor and the memory subsystem, the control register comprising a plurality of bits, each bit associated with one of the plurality of memories; and

a power controller coupled to the processor and the memory subsystem, the power controller configurable to control the power state of at least part of the memory subsystem;

wherein the processor asserts a bit associated with a first memory of the plurality of memories, and the controller asserts a power control signal transmitted to the memory subsystem; and

wherein the asserted bit causes at least part of the first memory to operate at a first power level, and the control signal asserted by the memory controller causes a second memory of the plurality of memories to operate at a second power level associated with a power consumption level different from that of the first power level.

11. The IC of claim 10, wherein software executing on the processor core causes the processor to assert the bit associated with the first memory.

12. The IC of claim 10, further comprising a plurality of processor cores, each processor core coupled to the control register, and each processor core configurable to control the state of one or more bits within the control register.

13. The IC of claim 10, wherein the first and second power levels are each set to at least one power level selected from the group consisting of a full-power level, a reduced-power level, and a powered-down level.

14. The IC of claim 10, wherein each memory of the plurality of memories comprises an array and periphery logic, and wherein power provided to the array of each memory is controlled independently of power provided to the periphery logic of each memory.

15. The IC of claim 10, wherein the bit associated with the memory is further associated with the array.

16. The IC of claim 10, wherein the bit associated with the memory is further associated with the periphery logic.

17. A method, comprising:

configuring each of a subset of components of a subsystem to operate at a first power level;

signaling, to at least the subset of components, a transition to a second power level in which the subsystem consumes power at a rate different from that consumed when operating at the first power level; and

the subset of components operating at the first power level, and the configuring of each subset overriding the signaling to transition to the second power level.

18. The method of claim 17, wherein the signaling causes at least one component not included within the subset of components to operate at the second power level.

19. The method of claim 17, wherein the first and second power levels are each set to at least one power level selected from the group consisting of a full-power level, a reduced-power level, and a powered-down level.

20. The method of claim 17, wherein the configuring of each of the subset of components comprises asserting bits within a control register, each bit uniquely associated with a single component of the subset of components.