PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL FAULTS FROM PRODUCTION TEST DATA

• US 20080091981A1
• Filed: 03/06/2007
• Published: 04/17/2008
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Inovys Corp. (Advantest Corporation)
• Inventors: Chan, Gerald S., Potter, John C., Crouch, Alfred L., DOKKEN, RICHARD C.
• Granted Patent: US 8,615,691 B2
• Time in Patent Office: Days
• US Class Current: 714/45
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. A method for classifying faults into the following classes “

RAW STUCK”

, “

UNRESOLVED BROKEN CHAIN”

, “

RESOLVED BROKEN CHAIN”

, “

RAW DELAY”

, “

PATH DELAY”

, comprising the steps of

applying a chain integrity test pattern;

analyzing a chain integrity test pattern data log;

applying a stuck test pattern;

applying an AC-scan test pattern;

analyzing an AC-scan test pattern data log; and

identifying a path delay fault.

6. A method for localizing faults to within a detailed circuit description comprising the steps of:

classifying a fault;

translating a fault location from scan chain-bit position to a logical design name for a scan cell;

tracing components attached to a scan cell; and

reading a list of origins and dimensions of components and wires connecting said components.

7. The method of claim 6 for tracing fanout, wherein tracing components attached to a scan cell comprises the steps following:

discovering the component name that the port belongs to and compare it to the components in the component trace cache;

if a match is found, stop tracing this branch and continue tracing any unresolved branches;

if no match found, adding component name to the component trace cache

finding the net connected to the output port;

looking for input port(s) or inout port(s) connected to the net;

for each input port found checking to see if the component instance name associated with the input port or the input port itself is part of a trace filter, if yes, performing filter dependent actions;

checking to see if the component instance MACRO name is part of a trace control list;

using the LEF database, discovering the output ports on the component that belongs to the input port that is being processed;

and

for each output port found, repeating until all trace control points have been identified and/or until filter actions are performed.

8. The method of claim 6 for tracing fanin , wherein tracing components attached to a scan cell comprises the steps following:

discovering the component name that the port belongs to and compare it to the components in the component trace cache, if a match is found, stop tracing this branch and continue tracing any unresolved branches, if no match found, add component name to the component trace cache;

finding the net connected to the input port;

reading output port(s) or inout port(s) connected to the net, if more than one output port exists, issuing warnings because this is a potential bus contention mechanism which may cause a device to fail;

checking if the component instance name associated with the output port found in step 2 or the output port itself is part of a trace filter, if yes, perform filter dependent actions;

checking if the component instance MACRO name is part of a trace control list, if yes, stop tracing this branch;

discovering the input ports on the component that belongs to the output port found on the net; and

for each input port repeating above steps until all trace control points have been identified and/or until filter actions have been performed.

9. The method of claim 6 for tracing treetrace, wherein tracing components attached to a scan cell comprises the steps following:

identifying a starting scancell;

tracing the clock input back to the output of the first buffer;

tracing the output of said buffer to all components touched by this output;

repeating for a user defined number of buffer levels; and

filtering the returned elements for commonality amongst failing scancells.

10. The method of claim 6 for tracing netprint, wherein tracing components attached to a scan cell comprises the steps following:

looking up the port name;

finding the name of the net attached to it; and

retrieving the route XY coordinates, vias, and component port connection list.

11. The method of claim 6 further comprising controlling trace by at least one of:

setting limits for the trace activity,

modifying the result of the trace,

normalizing hierarchy symbols, and

matching deviant hierarchy names.

12. The method of claim 6 further comprising building a high performance interactive database comprising the following steps:

parsing at least one LEF file;

parsing at least one DEF file

merging a plurality of DEF files;

concatenating hierarchy names;

recalculating XY coordinates

recalculating orientation facings;

merging nets; and

storing the netlist of the design in a query-able form for tracing.

13. The method of claim 12 further comprising the step of storing a query-able database file comprising the steps of storing a major syntax block contained in any LEF file and/or any DEF file in a key-value context by using the item name as the key and the LEF or DEF description statement as the value, wherein the key further comprises:

Port instance name, Net instance name, Component instance name, MACRO name (a.k.a., model name, module name, etc.) ,VIA name and MACRO names that have been used as ScanCells, wherein values to the keys are comprised one of a key to other database and a full content description of a DEF or LEF entry.

14. The method of claim 13 wherein a database file is a multi-dimensional database enabling multi-dimensional query of the LEF MACROs, PIN names, and I/O direction.

15. A method for reporting the physical area containing an electrically detected fault recorded on semiconductor test equipment apparatus to a computer-implemented yield management utility software program product comprising the following steps:

localizing faults to within a detailed circuit description; and

exporting X/Y Die Coordinate on Wafer, X/Y Origin on Die, X size, Y size, Area (X*Y) and Classification.

16. A method for displaying the geometric location of potential defect locations with circuit details corresponding to a fault, graphically on a computer-attached display apparatus comprising the following steps:

adjusting the width of a line representing a wire to be visible on the display;

computing a scaling factor to fully show on the display the geometric location of potential defect locations on a die on a wafer;

displaying each component on a list of potential defect locations in scaled origin, width, and length; and

displaying the adjusted lines representing wires on the list of potential defect locations.