TEST SYSTEM FOR INTEGRATED CIRCUITS

• US 20080091994A1
• Filed: 12/13/2007
• Published: 04/17/2008
• Est. Priority Date: 09/10/1999
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dean, Alvar, Ventrone, Sebastian
• Granted Patent: US 7,478,280 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/31932 Comparators

Abstract

A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

Claims

1. A method for simultaneously transporting and testing integrated circuit chips comprising:

connecting integrated circuit chips to test boards having test circuitry;

mounting said test boards in test boxes having power supplies;

mounting said test boxes in an in-transit box;

transporting said integrated circuit chips in said in-transit box;

testing said integrated circuit chips during said transporting by using said test circuitry; and

supplying power to said integrated circuit chips during said transporting and said testing by using said power supplies.

2. The method in claim 1, all the limitations of which are incorporated herein by reference, further comprising identifying ones of said integrated circuit chips which failed said testing.

3. The method in claim 2, all the limitations of which are incorporated herein by reference, wherein said identifying comprises storing results of said testing in a memory.

4. The method in claim 2, all the limitations of which are incorporated herein by reference, wherein said identifying comprises displaying a visual indicator of passing or failing chips

5. The method in claim 2, all the limitations of which are incorporated herein by reference, wherein said testing includes comparing output signals of said integrated circuit chips with each other.

6. The method in claim 1, wherein said testing includes comparing output signals of one integrated circuit chip with output signals of all other integrated circuit chips that have not been identified as defective.

7. The method in claim 1, all the limitations of which are incorporated herein by reference, wherein said testing includes comparing output signals of said integrated circuit chips with a golden chip.