Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products

• US 20080092095A1
• Filed: 10/29/2007
• Published: 04/17/2008
• Est. Priority Date: 06/10/2003
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yashchin, Emmanuel, Trapp, Brian, Lanzerotti, Mary, Takken, Asya, Landers, Christina
• Granted Patent: US 7,752,581 B2
• Time in Patent Office: Days
• US Class Current: 702/185
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

Claims

1-34. -34. (canceled)

35. A method comprising:

obtaining defect characteristic data;

obtaining chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes;

specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor weighted in at least two degrees for a physical location of the defect characteristic data relative to the design shapes, wherein the risk factor relates to inoperability of an individual semiconductor chip;

estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data;

generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data;

applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and

outputting a predicted yield based on the applied probability model.

36. The method of claim 35, wherein the probability relationship comprises a risk map for the semiconductor chip.

37. The method of claim 36, further comprising:

generating a tool inspection area for the semiconductor chip as a function of the risk map; and

inspecting the tool inspection area for further defects on the semiconductor chip.

38. The method of claim 35, wherein the probability relationship comprises defect location risk, defect location, and defect size.

39. The method of claim 35, further comprising:

testing the semiconductor chip for compliance with the probability model; and

updating the probability relationship based on the testing.

40. The method of claim 35, wherein the probability relationship comprises an exponential function with the exponent being a smooth function of the defect characteristic data and one or more adjustable parameters.

41. The method of claim 40, wherein the defect characteristic data comprises at least one of defect type and defect size, and wherein the smooth function is further a smooth function of the at least one risk factor.

42. The method of claim 40, wherein the adjustable parameters are estimated based on defect and yield data of the probability model.

43. The method of claim 35, wherein the defect characteristic data-is obtained from an inspection of the semiconductor chip.

44. The method of claim 35, further comprising:

evaluating a semiconductor chip of the batch for inoperability using the probability model during an interim fabrication step of said chip.

45. The method of claim 44, wherein the evaluating is in real time with the interim fabrication step.

46. The method of claim 35, wherein outputting a predicted yield comprises outputting a number of wafer starts needed to meet a particular customer commitment.

47. The method of claim 35, further comprising:

ranking at least some defects of the list with a likelihood of being responsible for inoperability of a semiconductor chip.

48. A memory embodying a computer program that is readable by a computer for performing actions directed toward assessing a probability of failure of a semiconductor chip due to at least one defect, the actions comprising:

from inputs of defect characteristic data and chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes, specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor weighted in at least two degrees for a physical location of the defect characteristic data relative to the design shapes, wherein the risk factor relates to inoperability of an individual semiconductor chip;

estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data; and

generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data;

applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and

outputting a predicted yield based on the applied probability model.

49. The memory of claim 48, wherein the probability relationship comprises a risk map for the semiconductor chip.

50. The memory of claim 49, the actions further comprising:

generating a tool inspection area for the semiconductor chip as a function of the risk map.

51. The memory of claim 48, wherein the probability relationship comprises defect location risk, defect location, and defect size.

52. The memory of claim 48, the actions further comprising:

updating the probability relationship based on a feedback of actual testing of the semiconductor chip as compared to the probability model.

53. The memory of claim 48, wherein the probability relationship comprises an exponential function with the exponent being a smooth function of the defect characteristic data and one or more adjustable parameters.

54. The method of claim 53, wherein the defect characteristic data comprises at least one of defect type and defect size, and wherein the smooth function is further a smooth function of the at least one risk factor.

55. The method of claim 53, wherein the adjustable parameters are estimated based on defect and yield data of the probability model.

56. The memory of claim 48, the actions further comprising:

evaluating a semiconductor chip of the batch for inoperability using the probability model during an interim fabrication step of said chip.

57. The memory of claim 56, wherein the evaluating is in real time with the interim fabrication step.

58. The memory of claim 48, the actions further comprising:

wherein outputting a predicted yield comprises outputting a number of wafer starts needed to meet a particular customer commitment.

59. The memory of claim 48, the actions further comprising:

ranking at least some defects of the list with a likelihood of being responsible for inoperability of a semiconductor chip.