Semiconductor structure and process for forming ohmic connections to a semiconductor structure

• US 20080092944A1
• Filed: 10/16/2006
• Published: 04/24/2008
• Est. Priority Date: 10/16/2006
• Status: Abandoned Application

• Current Assignee: DAY4 Energy Incorporated
• Original Assignee: DAY4 Energy Incorporated
• Inventors: Rubin, Leonid
• Application Number:
  US11/581,769
• Publication Number:
  US 20080092944A1
• Time in Patent Office: Days
• US Class Current: 136/252
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A semiconductor apparatus is disclosed. The apparatus includes a first doped volume of semiconductor material, the first doped volume having a front surface and first and second adjacent regions. The first region has a first concentration of dopant and a first exposed area on the front surface. The second region has a second concentration of dopant and a second exposed area on the front surface, the second concentration being higher than the first concentration. The apparatus also includes a first external conductor and an alloy bonding the first external conductor to the second exposed area to ohmically connect the conductor to the second region.

Claims

1. A semiconductor apparatus comprising:

a first doped volume of semiconductor material, said first doped volume having a front surface and first and second adjacent regions;

said first region having a first concentration of dopant and a first exposed area on said front surface;

said second region having a second concentration of dopant and a second exposed area on said front surface, said second concentration being higher than said first concentration; and

a first external conductor; and

an alloy bonding said first external conductor to said second exposed area to ohmically connect said conductor to said second region.

2. The apparatus of claim 1 wherein said first region has a sheet resistance in the range of between about 80 ohms/sq to about 150 ohms/sq.

3. The apparatus of claim 1 wherein second region has a sheet resistance in the range of between about 0.5 ohms/sq to about 40 ohms/sq.

4. The apparatus of claim 1 wherein said second region comprises a plurality of separate second regions, each of said separate second regions generally having a concentration of dopant approximately equal to said second concentration and each of said separate second regions having a respective second exposed surface.

5. The apparatus of claim 4 wherein said first external conductor is bonded to said second exposed areas of at least two of said plurality of second regions.

6. The apparatus of claim 4 wherein said regions of said plurality of second regions are distributed across said front surface.

7. The apparatus of claim 4 wherein said regions of said plurality of second regions are distributed across said front surface in parallel spaced apart rows.

8. The apparatus of claim 7 wherein said regions in a first parallel spaced apart row are staggered relative to said regions in a second adjacent parallel row.

9. The apparatus of claim 7 wherein said first external conductor comprises a plurality of conductors, each of said plurality of conductors being bonded to a plurality of said second exposed areas of respective said second regions in one of said plurality of parallel rows.

10. The apparatus of claim 1 wherein said first external conductor comprises at least one of silver, copper, and alloys thereof.

11. The apparatus of claim 1 wherein said first external conductor comprises a wire having a diameter of between about 30 microns and about 200 microns.

12. The apparatus of claim 1 wherein said first external conductor comprises at least a portion having a cross sectional shape that is generally circular or generally rectangular or generally triangular.

13. The apparatus of claim 1 wherein a portion of said first external conductor is adhered to a polymeric film and wherein said polymeric film is adhered to said front surface.

14. The apparatus of claim 13 wherein said polymeric film comprises polyester.

15. The apparatus of claim 13 wherein said polymeric film has a thickness of between about 6 microns and about 100 microns.

16. The apparatus of claim 13 further comprising an adhesive between said polymeric film and said front surface, said adhesive being operable to adhere said polymeric film to said front surface.

17. The apparatus of claim 16 wherein said adhesive has thermoplastic properties.

18. The apparatus of claim 16 wherein said adhesive becomes fluid when subjected to a temperature in the range of between about 60 degrees Celsius and about 170 degrees Celsius.

19. The apparatus of claim 16 wherein said adhesive becomes fluid when subjected to a temperature in the range of between about 80 degrees Celsius and about 150 degrees Celsius.

20. The apparatus of claim 16 wherein said adhesive has a thickness of between about 20 microns and about 200 microns.

21. The apparatus of claim 1 wherein said alloy comprises a composition comprising at least two of:

Ag, Bi, Cd, Ga, In, Pb, Sb, Sn, and Zn.

22. The apparatus of claim 20 wherein said alloy comprises In, Sn, and Ag in a proportion of about 47% In, about 51% Sn, and about 2% Ag.

23. The apparatus of claim 20 wherein said alloy comprises In and Sn in a proportion of about 48% In and about 52% Sn.

24. The apparatus of claim 1 wherein said alloy has a thickness of between about 1 micron and about 5 microns.

25. The apparatus of claim 1 wherein said alloy has a melting temperature of between about 30 degrees Celsius and about 200 degrees Celsius.

26. The apparatus of claim 1 wherein said alloy has a melting temperature of between about 60 degrees Celsius and about 150 degrees Celsius.

27. The apparatus of claim 1 further comprising a layer of dielectric material between said alloy and said second exposed area, said layer of dielectric material being operable to passivate said second exposed area and being sufficiently thin to permit charge carriers to tunnel through said layer of dielectric material between said second exposed area and said alloy.

28. The apparatus of claim 27 wherein said dielectric material comprises silicon nitride or silicon dioxide.

29. The apparatus of claim 27 wherein said layer of dielectric material has a thickness of less than about 2 nanometers.

30. The apparatus of claim 4 further comprising interconnecting regions extending between at least some of said second regions, said interconnecting regions having a dopant concentration approximately equal to said second dopant concentration, said interconnecting regions being operable to interconnect said second regions within said first doped volume.

31. The apparatus of claim 1 wherein said first doped volume has a first dopant polarity and wherein said apparatus further comprises a second doped volume of semiconductor material adjacent to said first doped volume and having a opposite dopant polarity to said first dopant polarity, said first and second volumes of semiconductor material forming a p/n junction therebetween.

32. The apparatus of claim 31 wherein said p/n junction is operably configured to separate charge carriers in response to irradiation of the apparatus by light.

33. The apparatus of claim 32 further comprising an antireflective layer on said front surface, said antireflective layer having an opening aligned with said second exposed area, said antireflective layer being operably configured to facilitate coupling of said light into said semiconductor apparatus.

34. The apparatus of claim 1 further comprising a passivation layer on said front surface, said passivation layer having an opening aligned with said second exposed area.

35. The apparatus of claim 31 wherein said second doped volume comprises:

a back surface and third and fourth regions;

said third region having a third concentration of dopant and a third exposed area on said back surface;

said fourth region having a fourth concentration of dopant and a fourth exposed area on said back surface, said fourth concentration being higher than said third concentration.

36. The apparatus of claim 35 wherein said third region has a sheet resistance in the range of between about 20 ohms/sq to about 60 ohms/sq.

37. The apparatus of claim 35 wherein fourth region has a sheet resistance in the range of between about 0.1 ohms/sq to about 20 ohms/sq.

38. The apparatus of claim 35 further comprising:

a second external conductor;

an alloy on said second external conductor, said alloy bonding said second conductor to said fourth exposed area to ohmically connect said second conductor to said fourth region.

39. The apparatus of claim 35 wherein said fourth region comprises a plurality of separate fourth regions, each of said separate fourth regions generally having a concentration of dopant approximately equal to said fourth concentration and each of said fourth regions having a corresponding fourth exposed surface.

40. A semiconductor apparatus comprising:

a first doped volume of semiconductor material, said first doped volume having a front surface and first and second adjacent regions;

said first region having a first concentration of dopant and a first exposed area on said front surface;

said second region having a second concentration of dopant and a second exposed area on said front surface, said second concentration being higher than said first concentration; and

a first external conductor; and

first means for bonding said first external conductor to said second exposed area to ohmically connect said first conductor to said second region.

41. The apparatus of claim 40 wherein said first means for bonding comprises an alloy.

42. The apparatus of claim 40 further comprising first means for holding said first external conductor.

43. The apparatus of claim 42 wherein said first means for holding comprises a first polymeric film and a first adhesive securing said first conductor to said first polymeric film.

44. The apparatus of claim 43 wherein said first adhesive is operably configured to secure said first polymeric film to said front surface.

45. The apparatus of claim 40 further comprising means for passivating said second exposed area.

46. The apparatus of claim 45 wherein said means for passivating comprises a layer of dielectric material between said second exposed area and said means for bonding.

47. The apparatus of claim 43 wherein said second regions include a plurality of second regions, each having a respective second exposed surface and wherein said apparatus further comprises means for interconnecting at least some of said second regions together.

48. The apparatus of claim 47 wherein said means for interconnecting comprises means for interconnecting regions having a dopant concentration approximately equal to said second dopant concentration.

49. The apparatus of claim 40 wherein said first doped volume has a first dopant polarity and wherein said apparatus further comprises a second doped volume of semiconductor material adjacent to said first doped volume and having a second dopant polarity opposite to said first dopant polarity, said first and second volumes of semiconductor material forming a p/n junction therebetween.

50. The apparatus of claim 49 wherein said second doped volume comprises:

a back surface and third and fourth regions;

said third region having a third concentration of dopant and a third exposed area on said back surface; and

said fourth region having a fourth concentration of dopant and a fourth exposed area on said back surface, said fourth concentration being higher than said third concentration.

51. The apparatus of claim 50 further comprising:

a second external conductor; and

second means for bonding said second conductor to said fourth exposed area to ohmically connect said second conductor to said fourth region.

52. The apparatus of claim 51 wherein said second means for bonding includes an alloy.

53. The apparatus of claim 51 further comprising second means for holding said second external conductor.

54. The apparatus of claim 53 wherein said second means for holding comprises a second polymeric film and a second adhesive securing said second conductor to said second polymeric film.

55. The apparatus of claim 54 wherein said second adhesive is operably configured to secure said second polymeric film to said back surface.

56. A process for making an electrical connection to a semiconductor structure comprising a first doped volume of semiconductor material, said first doped volume having a front surface and first and second adjacent regions, said first region having a first concentration of dopant and a first exposed area on said front surface, said second region having a second concentration of dopant and a second exposed area on said front surface, said second concentration being higher than said first concentration, the process comprising:

bonding a first external conductor to said second exposed area to ohmically connect said first conductor to said second region.

57. The process of claim 56 wherein bonding comprises melting an alloy between said first external conductor and said second exposed area.

58. The process of claim 56 further comprising holding said first external conductor.

59. The process of claim 58 wherein holding comprises adhesively securing said first conductor to a first polymeric film.

60. The process of claim 59 further comprising securing said first polymeric film to said front surface.

61. The process of claim 56 further comprising passivating said second exposed area.

62. The process of claim 61 wherein passivating comprises forming a layer of dielectric material on said first surface, prior to bonding.

63. The process of claim 59 further comprising interconnecting together at least some of a plurality of separate said second regions.

64. The process of claim 63 wherein interconnecting comprises doping said semiconductor structure to form interconnecting regions between said separate second regions, said interconnecting regions having a dopant concentration approximately equal to said second dopant concentration.

65. The process of claim 56 wherein said first doped volume has a first dopant polarity and wherein said semiconductor structure further comprises a second doped volume of semiconductor material adjacent to said first doped volume and having a opposite dopant polarity to said first dopant polarity, said first and second volumes of semiconductor material forming a p/n junction therebetween, said second doped volume comprising a back surface and third and fourth regions, said third region having a third concentration of dopant and a third exposed area on said back surface, said fourth region having a fourth concentration of dopant and a fourth exposed area on said back surface, said fourth concentration being higher than said third concentration, and wherein said process further comprises bonding a second external conductor to said fourth exposed area to ohmically connect said second conductor to said fourth region.

66. The process of claim 65 wherein bonding said second conductor comprises melting an alloy between said second conductor and said fourth exposed area.

67. The process of claim 65 further comprising holding said second external conductor.

68. The process of claim 67 wherein holding said second external conductor comprises adhesively securing said second external conductor to a second polymeric film.

69. The process of claim 68 further comprising adhesively securing said second polymeric film to said back surface of said semiconductor structure.

70. In a semiconductor structure having a first doped volume of semiconductor material, the first doped volume having a front surface and first and second adjacent regions, the first region having a first concentration of dopant and a first exposed area on the front surface, the second region having a second concentration of dopant and a second exposed area on the front surface, the second concentration being higher than the first concentration, a process for forming electrical connections to the semiconductor structure comprises:

cleaning the second exposed area on the front surface of the semiconductor material;

pressing a first external conductor coated with an alloy into contact with the second exposed area, while heating said alloy to a temperature sufficient to at least partially melt said alloy; and

maintaining said pressing while cooling said alloy to cause said alloy to solidify, thereby bonding said first conductor to said second exposed area such that said first conductor is in ohmic contact with said second region.

71. The process of claim 70 wherein cleaning comprises etching the front surface to remove oxides from the second exposed area.

72. The process of claim 70 wherein pressing comprises pressing to a pressure of between about 0.1 bar and about 1 bar.

73. The process of claim 70 wherein heating comprises heating the structure to cause said alloy to be heated to a temperature of between about 30 degrees Celsius and about 200 degrees Celsius.

75. The process of claim 70 wherein said conductor is adhered to a polymeric film and wherein pressing comprises pressing said conductor into contact with the second exposed area.

76. The process of claim 75 wherein pressing further comprises adhering said polymeric film to the front surface.

77. The process of claim 75 wherein said semiconductor structure comprises an antireflective layer on said first exposed surfaces and wherein pressing further comprises adhering said polymeric film to at least a portion of said antireflective layer.

78. The process of claim 70 further comprising forming a passivation layer on said second exposed area and wherein pressing comprises pressing said first conductor such that said alloy bonds the conductor to said second region through said passivation layer.

79. The process of claim 78 wherein forming said passivation layer comprises forming a layer of dielectric material on said second exposed area.

80. The process of claim 79 wherein forming said layer of dielectric material comprises forming a layer of silicon nitride or silicon dioxide on said second exposed area.

81. The process of claim 80 wherein forming said layer of dielectric material comprises forming a layer of dielectric material such that said layer has a thickness of about 2 nanometers or less.

74. The process of clam 39 wherein heating comprises heating the structure to cause said alloy to be heated to a temperature of between about 60 degrees Celsius and about 150 degrees Celsius.