MULTILAYER CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

• US 20080093117A1
• Filed: 01/03/2008
• Published: 04/24/2008
• Est. Priority Date: 07/12/2005
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: YOSHIKAWA, Takayoshi, OIKAWA, Yoshikazu
• Granted Patent: US 7,847,197 B2
• Time in Patent Office: Days
• US Class Current: 174/262
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0265 characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0352 : Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/09227 : Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09736 : Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0156 : Temporary polymeric carrier or foil, e.g. for processing or transferring
• CPC Class Codes: H05K 3/0029 : of inorganic insulating material
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/4611 : by laminating two or more circuit boards H05K3/4652 takes precedence
• CPC Class Codes: H05K 3/4629 : laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A multilayer circuit board includes a laminate having a plurality of ceramic layers, and a wiring pattern disposed in the laminate, wherein a ceramic layer includes, as the wiring pattern, a fully penetrating via-hole conductor that vertically passes through the ceramic layers, and a serial partially penetrating via-hole conductor that is electrically connected to the fully penetrating via-hole conductor in the ceramic layers and does not pass completely through the ceramic layers.

Claims

1. A multilayer circuit board comprising:

a laminate including a plurality of substrate layers; and

a wiring pattern disposed in the laminate;

wherein

at least one layer of the plurality of substrate layers includes, as the wiring pattern, at least one fully penetrating via-hole conductor that vertically passes through the substrate layer, and at least one partially penetrating via-hole conductor that is electrically connected to the fully penetrating via-hole conductor in the substrate layer and does not pass completely through the substrate layer.

2. The multilayer circuit board according to claim 1, wherein the at least one partially penetrating via-hole conductor is at least one serial partially penetrating via-hole conductor including a plurality of partially penetrating via-hole conductors.

3. The multilayer circuit board according to claim 2, wherein the substrate layer that includes the at least one fully penetrating via-hole conductor and the at least one serial partially penetrating via-hole conductor is disposed at the top of the laminate.

4. The multilayer circuit board according to claim 3, wherein the substrate layer that includes the at least one fully penetrating via-hole conductor and the at least one serial partially penetrating via-hole conductor is arranged such that the serial partially penetrating via-hole conductor is disposed on the bottom, and an end surface of the fully penetrating via-hole conductor on a top surface of the substrate layer is arranged to be connected to a connection terminal of a surface mount device to be mounted on the substrate layer.

5. The multilayer circuit board according to claim 2, wherein the at least one fully penetrating via-hole conductor is connected to at least one in-plane conductor of the substrate layer through the at least one serial partially penetrating via-hole conductor.

6. The multilayer circuit board according to claim 2, wherein the at least one fully penetrating via-hole conductor includes a first fully penetrating via-hole conductor and a second fully penetrating via-hole conductor, the first fully penetrating via-hole conductor and the second fully penetrating via-hole conductor being adjacent to each other, and a first serial partially penetrating via-hole conductor connected to the first fully penetrating via-hole conductor extends away from the second fully penetrating via-hole conductor.

7. The multilayer circuit board according to claim 6, wherein a second serial partially penetrating via-hole conductor connected to the second fully penetrating via-hole conductor extends away from the first fully penetrating via-hole conductor.

8. The multilayer circuit board according to claim 6, wherein the at least one fully penetrating via-hole conductor further includes a third fully penetrating via-hole conductor, which is adjacent to the first fully penetrating via-hole conductor or the second fully penetrating via-hole conductor, wherein a third serial partially penetrating via-hole conductor connected to the third fully penetrating via-hole conductor extends away from the first fully penetrating via-hole conductor and the second fully penetrating via-hole conductor.

9. The multilayer circuit board according to claim 1, wherein the substrate layer is composed of a low-temperature co-fired ceramic material, and the wiring pattern is composed of an electroconductive material mainly composed of silver or copper.

10. A method for manufacturing a multilayer circuit board that includes a laminate of a plurality of substrate layers and a wiring pattern disposed in the laminate, the method comprising:

a first step of forming a through hole that vertically passes through at least one layer of the plurality of substrate layers, and at least one semi-through hole that is in contact with the through hole and does not pass completely through the substrate layer; and

a second step of filling the through hole and the at least one semi-through hole with an electroconductive material to form a fully penetrating via-hole conductor and a partially penetrating via-hole conductor as the wiring pattern.

11. The method for manufacturing a multilayer circuit board according to claim 10, wherein the at least one semi-through hole is a serial semi-through hole formed of a plurality of semi-through holes, and a serial partially penetrating via-hole conductor is formed from the serial semi-through hole.

12. The method for manufacturing a multilayer circuit board according to claim 11, further comprising the step of irradiating the substrate layer with a laser beam to form the through hole and the serial semi-through hole.

13. The method for manufacturing a multilayer circuit board according to claim 12, further comprising the steps of supporting the substrate layer with a carrier film, and irradiating the substrate layer with a laser beam from the carrier film side to form the through hole and the serial semi-through hole.

14. The method for manufacturing a multilayer circuit board according to claim 12, further comprising the steps of supporting the substrate layer with a carrier film, and irradiating the substrate layer with a laser beam from the substrate layer side to form the through hole and the serial semi-through hole.

15. The method for manufacturing a multilayer circuit board according to claim 10, further comprising a third step of preparing a green laminate that includes the substrate layer and firing the green laminate, wherein the substrate layer in the first step and the second step is a green ceramic sheet.