Wireless Chip And Manufacturing Method Thereof

• US 20080093464A1
• Filed: 08/10/2005
• Published: 04/24/2008
• Est. Priority Date: 08/23/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Maruyama, Junya, Sugiyama, Eiji, Dozen, Yoshitaka, Dairiki, Koji, Tamura, Tomoko
• Granted Patent: US 8,288,773 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.

Claims

1. A thin film integrated circuit comprising:

a first insulating layer;

at least a first thin film transistor and a second thin film transistor provided over the first insulating layer;

a second insulating layer covering the first thin film transistor and the second thin film transistor;

a first conductive layer over the second insulating layer and functioning as at least one of a source wiring and a drain wiring;

a third insulating layer covering the first conductive layer;

an antenna comprising a second conductive layer over the third insulating layer; and

a fourth insulating layer covering the antenna,

wherein a first semiconductor layer included in the first thin film transistor has a first channel forming region and a first impurity region, and

wherein a second semiconductor layer included in the second thin film transistor has a second channel forming region and a second impurity region.

3. The thin film integrated circuit according to claim 1 or 2, wherein each channel length of the first semiconductor layer and the second semiconductor layer is 1 μ

m to 3 μ

m.

4. The thin film integrated circuit according to claim 1 or 2, wherein a gate electrode included in each of the first thin film transistor and the second thin film transistor comprises a tantalum nitride layer and a tungsten layer over the tantalum nitride layer.

5. The thin film integrated circuit according to claim 1 or 2, wherein the first conductive layer comprises a first titanium layer, an aluminum layer added with silicon over the first titanium layer, and a second titanium layer over the aluminum layer added with silicon.

6. The thin film integrated circuit according to claim 1 or 2, wherein the first conductive layer comprises a titanium nitride layer, a first titanium layer over the titanium nitride layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer.

7. The thin film integrated circuit according to claim 1 or 2, wherein the second conductive layer comprises an aluminum layer.

8. The thin film integrated circuit according to claim 1 or 2, wherein the second conductive layer comprises a titanium layer and an aluminum layer over the titanium layer.

9. The thin film integrated circuit according to claim 1 or 2, wherein the first insulating layer comprises a silicon oxide layer, a silicon nitride oxide layer over the silicon oxide layer, and a silicon oxynitride layer over the silicon nitride oxide layer.

10. The thin film integrated circuit according to claim 1 or 2, wherein the first insulating layer comprises a first silicon oxynitride layer, a silicon nitride oxide layer over the first silicon oxynitride layer, and a second silicon oxynitride layer over the silicon nitride oxide layer.

11. The thin film integrated circuit according to claim 1 or 2, wherein the first insulating layer comprises a silicon nitride oxide layer and silicon oxynitride layer over the silicon nitride oxide layer.

12. The thin film integrated circuit according to claim 1 or 2, wherein the second insulating layer comprises an inorganic layer of a single layer or a stacked layer.

13. The thin film integrated circuit according to claim 1 or 2, wherein the third insulating layer comprises an organic layer and an inorganic layer over the organic layer.

14. The thin film integrated circuit according to claim 1 or 2, wherein the third insulating layer comprises an inorganic layer of a single layer or a stacked layer.

15. The thin film integrated circuit according to claim 1 or 2, wherein the fourth insulating layer comprises an organic layer.

16. The thin film integrated circuit according to claim 1 or 2 is provided between a first base material and a second base material, wherein one or both of the first base material and the second base material comprise an adhesive layer on one surface.

2. A thin film integrated circuit comprising:

a first insulating layer;

at least a first thin film transistor and a second thin film transistor provided over the first insulating layer;

a second insulating layer covering the first thin film transistor and the second thin film transistor;

a first conductive layer over the second insulating layer and functioning as at least one of a source wiring and a drain wiring;

a third insulating layer covering the first conductive layer;

an antenna comprising a second conductive layer over the third insulating layer; and

a fourth insulating layer covering the antenna,

wherein the first thin film transistor has a sidewall insulating layer,

wherein a first semiconductor layer included in the first thin film transistor has a first channel forming region, a first impurity region, and a second impurity region,

wherein a second semiconductor layer included in the second thin film transistor has a second channel forming region and a third impurity region,

wherein the concentration of an impurity element in the first impurity region is lower than the concentration of an impurity element in the second impurity region, and

wherein the sidewall insulating layer is in contact with a side surface of a gate electrode layer and is overlapped with the first impurity region.

17. A method for manufacturing a thin film integrated circuit comprising the steps of:

forming a peeling layer over a substrate;

forming a first insulating layer over the peeling layer;

forming at least a first crystalline semiconductor layer and a second crystalline semiconductor layer over the first insulating layer;

forming a gate insulating layer over the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming at least a first gate electrode and a second gate electrode over the first crystalline semiconductor layer and the second crystalline semiconductor layer with the gate insulating layer interposed therebetween;

forming a first n-type impurity region by adding an impurity element into the first crystalline semiconductor layer, using the first conductive layer as a mask;

forming a first p-type impurity region by adding an impurity element into the second crystalline semiconductor layer, using the first conductive layer as a mask;

forming at least one sidewall insulating layer in contact with a side surface of the first gate electrode and overlapped with a part of the first n-type impurity region;

forming a second n-type impurity region and a third n-type impurity region by adding an impurity element into the first n-type impurity region, using the sidewall insulating layer as a mask;

forming a second insulating layer over the first conductive layer,

forming a second conductive layer being over the second insulating layer and functioning as at least one wiring electrically connected to one of the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming a third insulating layer to cover the second conductive layer;

forming an antenna comprising a third conductive layer over the third insulating layer;

forming an opening by etching the first insulating layer, the gate insulating layer, the second insulating layer, and the third insulating layer to expose the peeling layer;

forming a fourth insulating layer to cover the antenna; and

peeling a thin film integrated circuit including at least a first thin film transistor and a second thin film transistor at least including the first crystalline semiconductor layer, the second crystalline semiconductor layer, the gate insulating layer, and the first conductive layer from the substrate by introducing etchant to the opening and removing the peeling layer.

21. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein the substrate is a glass substrate.

22. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein the substrate is a quartz substrate.

23. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein a layer containing tungsten or molybdenum is formed as the peeling layer.

24. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein a layer containing the oxide of tungsten or molybdenum is formed in an oxygen atmosphere by a sputtering method as the peeling layer.

25. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein a layer containing the oxide of tungsten (WO_x;

the value x satisfies 0<

x<

3) is formed in an oxygen atmosphere by a sputtering method as the peeling layer.

26. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein a layer containing tungsten or molybdenum is formed as the peeling layer and a layer containing the oxide of silicon is formed as the first insulating layer.

27. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein a layer containing silicon is formed as the peeling layer.

28. The method for manufacturing a thin film integrated circuit according to any one of claims 17 to 20, wherein the etchant is gas or liquid containing a compound comprising fluorine.

18. A method for manufacturing a thin film integrated circuit comprising the steps of:

forming a peeling layer over a substrate;

forming a first insulating layer over the peeling layer;

forming at least a first crystalline semiconductor layer and a second crystalline semiconductor layer over the first insulating layer;

forming a gate insulating layer over the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming at least a first gate electrode and a second gate electrode over the first crystalline semiconductor layer and the second crystalline semiconductor layer with the gate insulating layer interposed therebetween;

forming a first n-type impurity region by adding an impurity element into the first crystalline semiconductor layer, using the first conductive layer as a mask;

forming a first p-type impurity region by adding an impurity element into the second crystalline semiconductor layer, using the first conductive layer as a mask;

forming at least one sidewall insulating layer in contact with a side surface of the first gate electrode and overlapped with a part of the first n-type impurity region;

forming a second n-type impurity region and a third n-type impurity region by adding an impurity element into the first n-type impurity region, using the sidewall insulating layer as a mask;

forming a second insulating layer over the first conductive layer;

forming a second conductive layer over the second insulating layer and functioning as at least one wiring electrically connected to one of the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming a third insulating layer to cover the second conductive layer;

forming an antenna comprising a third conductive layer over the third insulating layer;

forming a fourth insulating layer to cover the antenna;

forming an opening by etching the first insulating layer, the gate insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer to expose the peeling layer, and

peeling a thin film integrated circuit including at least a first thin film transistor and a second thin film transistor at least including the first crystalline semiconductor layer, the second crystalline semiconductor layer, the gate insulating layer, and the first conductive layer from the substrate by introducing etchant to the opening and removing the peeling layer.

19. A method for manufacturing a thin film integrated circuit comprising the steps of:

forming a peeling layer over a substrate;

forming a first insulating layer over the peeling layer;

forming at least a first crystalline semiconductor layer and a second crystalline semiconductor layer over the first insulating layer;

forming a gate insulating layer over the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming at least a first gate electrode and a second gate electrode over the first crystalline semiconductor layer and the second crystalline semiconductor layer with the gate insulating layer interposed therebetween;

forming a first n-type impurity region by adding an impurity element into the first crystalline semiconductor layer, using the first conductive layer as a mask;

forming a first p-type impurity region by adding an impurity element into the second crystalline semiconductor layer, using the first conductive layer as a mask;

forming at least one sidewall insulating layer in contact with a side surface of the first gate electrode and overlapped with a part of the first n-type impurity region;

forming a second n-type impurity region and a third n-type impurity region by adding an impurity element into the first n-type impurity region, using the sidewall insulating layer as a mask;

forming a second insulating layer over the first conductive layer,

forming a second conductive layer over the second insulating layer and functioning as at least one wiring electrically connected to one of the first crystalline semiconductor layer and the second crystalline semiconductor layer,

forming a third insulating layer to cover the second conductive layer;

forming an antenna comprising a third conductive layer over the third insulating layer;

forming an opening by etching the first insulating layer, the gate insulating layer, the second insulating layer, and the third insulating layer to expose the peeling layer;

forming a fourth insulating layer to cover the antenna;

removing the peeling layer selectively by introducing etchant to the opening; and

peeling a thin film integrated circuit including at least a first thin film transistor and a second thin film transistor at least including the first crystalline semiconductor layer, the second crystalline semiconductor layer, the gate insulating layer, and the first conductive layer from the substrate by a physical force.

20. A method for manufacturing a thin film integrated circuit comprising the steps of:

forming a peeling layer over a substrate;

forming a first insulating layer over the peeling layer,

forming at least a first crystalline semiconductor layer and a second crystalline semiconductor layer over the first insulating layer;

forming a gate insulating layer over the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming at least a first gate electrode and a second gate electrode over the first crystalline semiconductor layer and the second crystalline semiconductor layer with the gate insulating layer interposed therebetween;

forming a first n-type impurity region by adding an impurity element into the first crystalline semiconductor layer, using the first conductive layer as a mask;

forming a first p-type impurity region by adding an impurity element into the second crystalline semiconductor layer, using the first conductive layer as a mask;

forming at least one sidewall insulating layer in contact with a side surface of the first gate electrode and overlapped with a part of the first n-type impurity region;

forming a second n-type impurity region and a third n-type impurity region by adding an impurity element into the first n-type impurity region, using the sidewall insulating layer as a mask;

forming a second insulating layer over the first conductive layer,

forming a second conductive layer over the second insulating layer and functioning as at least one wiring electrically connected to one of the first crystalline semiconductor layer and the second crystalline semiconductor layer;

forming a third insulating layer to cover the second conductive layer;

forming an antenna comprising a third conductive layer over the third insulating layer;

forming a fourth insulating layer to cover the antenna;

forming an opening by etching the first insulating layer, the gate insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer to expose the peeling layer;

removing the peeling layer selectively by introducing etchant to the opening; and

peeling a thin film integrated circuit including at least a first thin film transistor and a second thin film transistor at least including the first crystalline semiconductor layer, the second crystalline semiconductor layer, the gate insulating layer, and the first conductive layer from the substrate by a physical force.

29. A method for manufacturing a thin film integrated circuit comprising the steps of:

forming a peeling layer over a substrate;

forming a semiconductor device over the peeling layer, and

separating the semiconductor device from the substrate,

wherein the peeling layer comprises tungsten oxide (WO_x;

the value x satisfies 2≦

x<

3).