Thin film transistor for cross point memory and method of manufacturing the same

• US 20080093595A1
• Filed: 10/19/2007
• Published: 04/24/2008
• Est. Priority Date: 10/20/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, I-hun, Park, Young-soo, Kang, Dong-hun, Kim, Chang-jung, Lim, Hyuck
• Application Number:
  US11/976,008
• Publication Number:
  US 20080093595A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may be formed on a portion of the substrate. The gate insulation layer may be formed on the substrate and the gate. The channel includes ZnO and may be formed on the gate insulation layer over the gate. The source and the drain contact sides of the channel.

Claims

1. A thin film transistor, comprising:

a gate on a portion of a substrate;

a gate insulation layer on the substrate and the gate;

a channel including zinc oxide (ZnO) on the gate insulation layer over the gate; and

a source and a drain contacting opposing sides of the channel,

wherein the thin film transistor is used as a selection transistor for a three-dimensional stacking cross point memory.

2. The thin film transistor of claim 1, wherein the channel is formed of a compound including ZnO and at least one selected from the group consisting of gallium (Ga), indium (In), tin (Sn), aluminum (Al) and combinations thereof.

3. The thin film transistor of claim 2, wherein the compound is formed of gallium oxide (Ga₂O₃), indium oxide (In₂O₃) and ZnO.

4. The thin film transistor of claim 1, wherein the source is formed of a metal or a conductive oxide.

5. The thin film transistor of claim 4, wherein the metal is at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) and combinations thereof, and

the conductive oxide is at least one selected from the group consisting of indium-zinc oxide (IZO or InZnO), aluminum-zinc oxide (AZO or AlZnO) and combinations thereof.

6. The thin film transistor of claim 1, wherein the drain is formed of a metal or a conductive oxide.

7. The thin film transistor of claim 6, wherein the metal is at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) and combinations thereof, and

the conductive oxide is at least one selected from the group consisting of indium-zinc oxide (IZO or InZnO), aluminum-zinc oxide (AZO or AlZnO) and combinations thereof.

8. The thin film transistor of claim 1, wherein the channel has a thickness of 20 nm to 200 nm.

9. A method of manufacturing a thin film transistor, comprising:

forming a gate by depositing a conductive material on a portion of a substrate and patterning the deposited conductive material;

depositing a gate insulation layer on the substrate and the gate;

forming a channel on a portion of the gate insulation layer over the gate by depositing a channel material including zinc oxide (ZnO) on the gate insulation layer and patterning the deposited channel material; and

forming a source and a drain contacting opposing sides of the channel by depositing a conductive material on the channel and the gate insulation layer and patterning the conductive material,

wherein the thin film transistor is used as a selection transistor for a three-dimensional stacking cross point memory.

10. The method of claim 9, wherein the channel is formed by sputtering using a compound-target including ZnO and at least one selected from the group consisting of gallium (Ga), indium (In), tin (Sn), aluminum (Al) and combinations thereof.

11. The method of claim 10, wherein the compound-target includes gallium oxide (Ga₂O₃), indium oxide (In₂O₃) and ZnO.

12. The method of claim 9, wherein the channel is formed by co-sputtering using ZnO and at least one selected from the group consisting of gallium (Ga), indium (In), tin (Sn), aluminum (Al) and combinations thereof as targets.

13. The method of claim 9, wherein the source is a metal or a conductive oxide.

14. The thin film transistor of claim 13, wherein the metal is at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) and combinations thereof, and

the conductive oxide is at least one selected from the group consisting of indium-zinc oxide (IZO or InZnO), aluminum-zinc oxide (AZO or AlZnO) and combinations thereof.

15. The thin film transistor of claim 9, wherein the drain is formed of a metal or a conductive oxide.

16. The thin film transistor of claim 15, wherein the metal is at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) and combinations thereof, and

the conductive oxide is at least one selected from the group consisting of indium-zinc oxide (IZO or InZnO), aluminum-zinc oxide (AZO or AlZnO) and combinations thereof.

17. The method of claim 10, wherein the channel has a thickness of 20 nm to 200 nm.